K4D261638I-TC40,K4D261638I-TC40 pdf中文资料,K4D261638I-TC40引脚图,K4D261638I-TC40电路-Datasheet-电子工程世界

文档预览

K4D261638I

128M GDDR SDRAM

128Mbit GDDR SDRAM

2M x 16Bit x 4 Banks

Graphic Double Data Rate

Synchronous DRAM

Revision 1.2

November 2006

Notice

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

- 1 -

Rev. 1.2 November 2006

K4D261638I

Revision History

Revision

0.0

0.1

1.0

1.1

1.2

Month

March

May

August

January

November

Year

2005

2006

- Target Spec

- Defined target specification

- Corrected typo.

- Added CL2 feature in AC Characteristics.

- Finalized SPEC

- Deleted CL2.5 option

- Corrected typo.

History

128M GDDR SDRAM

- 2 -

Rev. 1.2 November 2006

K4D261638I

128M GDDR SDRAM

2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM

with Bi-directional Data Strobe and DLL

1.0 FEATURES

• 2.5V + 5% power supply for device operation

• 2.5V + 5% power supply for I/O interface

• SSTL_2 compatible inputs/outputs

• 4 banks operation

• MRS cycle with address key programs

-. Read latency 2,3(clock)

-. Burst length (2, 4 and 8)

-. Burst type (sequential & interleave)

• All inputs except data & DM are sampled at the positive going

edge of the system clock

• Differential clock input

• Wrtie-Interrupted by Read Function

• 2 DQS’s ( 1DQS / Byte )

• Data I/O transactions on both edges of Data strobe

• DLL aligns DQ and DQS transitions with Clock transition

• Edge aligned data & data strobe output

• Center aligned data & data strobe input

• DM for write masking only

• Auto & Self refresh

• 32ms refresh period (4K cycle)

• Lead free 66pin TSOP-II (RoHS compliant)

• Maximum clock frequency up to 250MHz

• Maximum data rate up to 500Mbps/pin

2.0 ORDERING INFORMATION

Part NO.

K4D261638I-LC40

K4D261638I-LC50

Max Freq.

250MHz

200MHz

Max Data Rate

500Mbps/pin

400Mbps/pin

Interface

SSTL_2

Package

66pin TSOP-II

* K4D261638I-TC is the Leaded package part number.

* For K4D261638I-LC50, VDD & VDDQ = 2.375V to 2.7V.

3.0 GENERAL DESCRIPTION

FOR 2M x 16Bit x 4 Bank DDR SDRAM

The K4D261638I is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabri-

cated with SAMSUNG

’

s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance

up to 1GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst

length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.

- 3 -

Rev. 1.2 November 2006

K4D261638I

4.0 PIN CONFIGURATION

(Top View)

DDQ

SSQ

DDQ

SSQ

DDQ

LDQS

LDM

CAS

RAS

AP/A

SSQ

DDQ

SSQ

DDQ

SSQ

UDQS

REF

UDM

CKE

128M GDDR SDRAM

66 PIN TSOP(II)

(400mil x 875mil)

(0.65 mm Pin Pitch)

PIN DESCRIPTION

CK,CK

CKE

RAS

CAS

L(U)DQS

L(U)DM

RFU

Differential Clock Input

Clock Enable

Chip Select

Row Address Strobe

Column Address Strobe

Write Enable

Data Strobe

Data Mask

Reserved for Future Use

, BA

~ DQ

DDQ

SSQ

Bank Select Address

Address Input

Data Input/Output

Power

Ground

Power for DQ’s

Ground for DQ’s

No Connection

- 4 -

Rev. 1.2 November 2006

K4D261638I

5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION

Symbol

CK, CK

Type

Input

Function

128M GDDR SDRAM

The differential system clock Input.

All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are

sampled on both edges of the DQS.

Activates the CK signal when high and deactivates the CK signal when low. By deactivating

the clock, CKE low indicates the Power down mode or Self refresh mode.

CS enables the command decoder when low and disabled the command decoder when high.

When the command decoder is disabled, new commands are ignored but previous operations

continue.

Latches row addresses on the positive going edge of the CK with RAS low. Enables row

access & precharge.

Latches column addresses on the positive going edge of the CK with CAS low. Enables col-

umn access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Data input and output are synchronized with both edge of DQS.

For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on

DQ8-DQ15.

Data in Mask. Data In is masked by DM Latency=0 when DM is

high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons

to the data on DQ8-DQ15.

Data inputs/Outputs are multiplexed on the same pins.

Selects which bank is to be active.

Row/Column addresses are multiplexed on the same pins.

Row addresses : RA

~ RA

, Column addresses : CA

~ CA

Power and ground for the input buffers and core logic.

Isolated power supply and ground for the output buffers to provide improved noise immunity.

Reference voltage for inputs, used for SSTL interface.

CKE

Input

RAS

CAS

Input

LDQS,UDQS

Input/Output

LDM,UDM

~ DQ

, BA

~ A

DDQ

SSQ

REF

NC/RFU

Input

Input/Output

Input

Power Supply

No connection/

This pin is recommended to be left "No connection" on the device

Reserved for future use

*1 : The timing reference point for the differential clocking is the cross point of CK and CK.

For any applications using the single ended clocking, apply V

REF

to CK pin.

- 5 -

Rev. 1.2 November 2006

参数对比

与K4D261638I-TC40相近的元器件有：K4D261638I-TC400、K4D261638I-LC500、K4D261638I-TC500、K4D261638I-LC50T、K4D261638I-LC400。描述及对比如下：

型号	K4D261638I-TC40	K4D261638I-TC400	K4D261638I-LC500	K4D261638I-TC500	K4D261638I-LC50T	K4D261638I-LC400
描述	DDR DRAM, 8MX16, 0.6ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66	DDR DRAM, 8MX16, 0.6ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66	DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66	DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66	DDR DRAM, 8MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66	DDR DRAM, 8MX16, 0.6ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66
是否Rohs认证	不符合	不符合	符合	不符合	符合	符合
包装说明	TSSOP, TSSOP66,.46	TSOP2, TSSOP66,.46	TSOP2, TSSOP66,.46	TSOP2, TSSOP66,.46	TSOP2, TSSOP66,.46	TSOP2, TSSOP66,.46
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
最长访问时间	0.6 ns	0.6 ns	0.7 ns	0.7 ns	0.7 ns	0.6 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	250 MHz	250 MHz	200 MHz	200 MHz	200 MHz	250 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
交错的突发长度	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8
JESD-30 代码	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66
长度	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm
内存密度	134217728 bit	134217728 bit	134217728 bit	134217728 bit	134217728 bit	134217728 bit
内存集成电路类型	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
内存宽度	16	16	16	16	16	16
功能数量	1	1	1	1	1	1
端口数量	1	1	1	1	1	1
端子数量	66	66	66	66	66	66
字数	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words
字数代码	8000000	8000000	8000000	8000000	8000000	8000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	65 °C	65 °C	65 °C	65 °C	65 °C	65 °C
组织	8MX16	8MX16	8MX16	8MX16	8MX16	8MX16
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSSOP	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
封装等效代码	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）	225	240	260	240	NOT SPECIFIED	260
电源	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	4096	4096	4096	4096	4096	4096
座面最大高度	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
自我刷新	YES	YES	YES	YES	YES	YES
连续突发长度	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8	2,4,8
最大待机电流	0.345 A	0.345 A	0.345 A	0.345 A	0.345 A	0.345 A
最大压摆率	0.39 mA	0.39 mA	0.39 mA	0.39 mA	0.39 mA	0.39 mA
最大供电电压 (Vsup)	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V
最小供电电压 (Vsup)	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V
标称供电电压 (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
表面贴装	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED	30	NOT SPECIFIED	30	NOT SPECIFIED	NOT SPECIFIED
宽度	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm
厂商名称	-	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)
零件包装代码	-	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
针数	-	66	66	66	66	66
JESD-609代码	-	e0	e6	e0	-	e6
端子面层	-	Tin/Lead (Sn/Pb)	Tin/Bismuth (Sn/Bi)	Tin/Lead (Sn/Pb)	-	Tin/Bismuth (Sn/Bi)