K4S511632C-KL75,K4S511632C-KL75 pdf中文资料,K4S511632C-KL75引脚图,K4S511632C-KL75电路-Datasheet-电子工程世界

文档预览

K4S511632C

CMOS SDRAM

DDP 512Mbit SDRAM

8M x 16bit x 4 Banks

Synchronous DRAM

LVTTL

Revision 0.1

Sept. 2001

This is to advise Samsung customers that in accordance with certain terms of an agreement, Samsung is prohibited from selling any DRAM

products configured in "Multi-Die Plastic" format for use as components in general and scientific computers, such as mainframes, servers,

work stations or desk top personal computers (hereinafter "Prohibited Computer Use"). Applications such as mobile, including cell phones,

telecom, including televisions and display monitors, or non-desktop computer systems, including laptops, notebook computers, are ,

however, permissible. "Multi-Die Plastic" is defined as two or more Dram die encapsulated within a single plastic leaded package

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 0.1 Sept. 2001

K4S511632C

CMOS SDRAM

Revision 0.0 (Mar., 2001)

Revision 0.1 (Sep., 2001)

•

Redefined IDD1 & IDD4 in DC Characteristics

Rev. 0.1 Sept. 2001

K4S511632C

8M x 16Bit x 4 Banks Synchronous DRAM

FEATURES

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock.

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period (8K Cycle)

Part No.

K4S511632C-KC/L7C

K4S511632C-KC/L75

K4S511632C-KC/L1H

K4S511632C-KC/L1L

CMOS SDRAM

GENERAL DESCRIPTION

The K4S511632C is 536,870,912 bits synchronous high data rate

Dynamic RAM organized as 4 x 8,392,608words by 16bits, fabri-

cated with SAMSUNG's high performance CMOS technology. Syn-

chronous design allows precise cycle control with the use of

system clock I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable burst length and

programmable latencies allow the same device to be useful for a

variety of high bandwidth, high performance memory system appli-

cations.

ORDERING INFORMATION

Max Freq.

133MHz(CL=2)

133MHz(CL=3)

100MHz(CL=2)

100MHz(CL=3)

LVTTL

54pin

TSOP(II)

Interface Package

FUNCTIONAL BLOCK DIAGRAM

I/O Control

LWE

Data Input Register

LDQM

Bank Select

2 x 4M x 16

Refresh Counter

Output Buffer

Row Decoder

Sense AMP

Row Buffer

DQi

A ddress Register

CLK

ADD

Column Decoder

Col. Buffer

LRAS

LCBR

Latency & Burst Length

LCKE

LRAS

LCBR

LWE

LCAS

Programming Register

LWCBR

LDQM

Timing Register

CLK

CKE

RAS

CAS

DQM

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 0.1 Sept. 2001

K4S511632C

PIN CONFIGURATION

(Top view)

DQ0

DDQ

DQ1

DQ2

SSQ

DQ3

DQ4

DDQ

DQ5

DQ6

SSQ

DQ7

LDQM

CAS

RAS

BA0

BA1

A10/AP

DQ15

SSQ

DQ14

DQ13

DDQ

DQ12

DQ11

SSQ

DQ10

DQ9

DDQ

DQ8

N.C/RFU

UDQM

CLK

CKE

A12

A11

CMOS SDRAM

54Pin TSOP (II)

(400mil x 875mil)

(0.8 mm Pin pitch)

PIN FUNCTION DESCRIPTION

CLK

Name

System cock

Chip select

Input Function

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

Row/column addresses are multiplexed on the same pins.

Row address : RA

~ RA

, Column address : CA

~ CA

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when L(U)DQM active.

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

This pin is recommended to be left No Connection on the device.

CKE

Clock enable

~ A

~ BA

RAS

CAS

L(U)DQM

D Q

Address

Bank select address

Row address strobe

Column address strobe

Write enable

Data input/output mask

Data input/output

Power supply/ground

Data output power/ground

No connection

/reserved for future use

DDQ

SSQ

N.C/RFU

Rev. 0.1 Sept. 2001

K4S511632C

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on V

supply relative to Vss

Storage temperature

Power dissipation

Short circuit current

Symbol

I N

, V

OUT

, V

DDQ

STG

Value

-1.0 ~ 4.6

-55 ~ +150

CMOS SDRAM

Unit

°C

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to V

= 0V, T

= 0 to 70°C)

Parameter

Supply voltage

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

Symbol

, V

DDQ

Min

3.0

2.0

-0.3

2.4

-10

Typ

3.3

3.0

Max

3.6

+0.3

0.8

0.4

Unit

= -2mA

= 2mA

Note

Notes :

1. V

I H

(max) = 5.6V AC. The overshoot voltage duration is

≤

3ns.

2. V

(min) = -2.0V AC. The undershoot voltage duration is

≤

3ns.

3. Any input 0V

≤

DDQ

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE

Clock

RAS, CAS , WE, DQM

Address, CS,CKE

D Q

~ DQ

= 3.3V, T

= 23°C, f = 1MHz, V

REF

=1.4V

200 mV)

Symbol

CLK

ADD

OUT

Min

5.0

4.0

Max

9.0

10.0

6.5

Unit

Note

Rev. 0.1 Sept. 2001

参数对比

与K4S511632C-KL75相近的元器件有：K4S511632C-KL1H、K4S511632C-KC1L、K4S511632C-KL1L、K4S511632C-KC7C、K4S511632C-KC75、K4S511632C-KC1H、K4S511632C-KL7C。描述及对比如下：

型号	K4S511632C-KL75	K4S511632C-KL1H	K4S511632C-KC1L	K4S511632C-KL1L	K4S511632C-KC7C	K4S511632C-KC75	K4S511632C-KC1H	K4S511632C-KL7C
描述	Synchronous DRAM, 32MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 32MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 32MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 32MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 32MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 32MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 32MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 32MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
零件包装代码	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
包装说明	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32
针数	54	54	54	54	54	54	54	54
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compli
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
最长访问时间	5.4 ns	6 ns	6 ns	6 ns	5.4 ns	5.4 ns	6 ns	5.4 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	133 MHz	100 MHz	100 MHz	100 MHz	133 MHz	133 MHz	100 MHz	133 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
交错的突发长度	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8
JESD-30 代码	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54
长度	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm
内存密度	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bi
内存集成电路类型	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
内存宽度	16	16	16	16	16	16	16	16
功能数量	1	1	1	1	1	1	1	1
端口数量	1	1	1	1	1	1	1	1
端子数量	54	54	54	54	54	54	54	54
字数	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words
字数代码	32000000	32000000	32000000	32000000	32000000	32000000	32000000	32000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	32MX16	32MX16	32MX16	32MX16	32MX16	32MX16	32MX16	32MX16
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
封装等效代码	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
电源	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	8192	8192	8192	8192	8192	8192	8192	8192
座面最大高度	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
自我刷新	YES	YES	YES	YES	YES	YES	YES	YES
连续突发长度	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP
最大待机电流	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A
最大压摆率	0.4 mA	0.38 mA	0.38 mA	0.38 mA	0.44 mA	0.4 mA	0.38 mA	0.44 mA
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
宽度	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm
厂商名称	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	-	-	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)