K4T56163QI
DDR2 SDRAM
256Mb I-die DDR2 SDRAM Specification
84FBGA with Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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DDR2 SDRAM
Table of Contents
1.0 Ordering Information ....................................................................................................................4
2.0 Key Features .................................................................................................................................4
3.0 Package Pinout/Mechanical Dimension & Addressing .............................................................5
3.1 x16 package pinout (Top View) : 84ball FBGA Package
.......................................................................5
3.2 FBGA Package Dimension(x16)
.......................................................................................................6
4.0 Input/Output Functional Description ..........................................................................................7
5.0 DDR2 SDRAM Addressing ...........................................................................................................8
6.0 Absolute Maximum DC Ratings ...................................................................................................9
7.0 AC & DC Operating Conditions ...................................................................................................9
7.1 Recommended DC Operating Conditions (SSTL - 1.8)
.........................................................................9
7.2 Operating Temperature Condition
..................................................................................................10
7.3 Input DC Logic Level
....................................................................................................................10
7.4 Input AC Logic Level
....................................................................................................................10
7.5 AC Input Test Conditions
..............................................................................................................10
7.6 Differential input AC logic Level
.....................................................................................................11
7.7 Differential AC output parameters
..................................................................................................11
8.0 ODT DC electrical characteristics .............................................................................................11
9.0 OCD default characteristics ......................................................................................................12
10.0 IDD Specification Parameters and Test Conditions ..............................................................13
11.0 DDR2 SDRAM IDD Spec ...........................................................................................................15
12.0 Input/Output capacitance .........................................................................................................16
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 ......................................16
13.1 Refresh Parameters by Device Density
........................................................................................16
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
.............................................16
13.3 Timing Parameters by Speed Grade
............................................................................................17
14.0 General notes, which may apply for all AC parameters ........................................................19
15.0 Specific Notes for dedicated AC parameters ..........................................................................21
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DDR2 SDRAM
Year
2007
- Initial Release
History
Revision History
Revision
1.0
Month
October
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K4T56163QI
1.0 Ordering Information
Org.
16Mx16
DDR2-800 5-5-5
K4T56163QI-ZC(L)E7
DDR2-800 6-6-6
K4T56163QI-ZC(L)F7
DDR2-667 5-5-5
K4T56163QI-ZC(L)E6
DDR2-533 4-4-4
K4T56163QI-ZC(L)D5
DDR2 SDRAM
DDR2-400 3-3-3
K4T56163QI-ZC(L)CC
Package
84 FBGA
Note :
1. Speed bin is in order of CL-tRCD-tRP
2. RoHS Compliant
2.0 Key Features
Speed
CAS Latency
tRCD(min)
tRP(min)
tRC(min)
DDR2-800 5-5-5
5
12.5
12.5
57.5
DDR2-800 6-6-6
6
15
15
60
DDR2-667 5-5-5
5
15
15
60
DDR2-533 4-4-4
4
15
15
60
DDR2-400 3-3-3
3
15
15
55
Units
tCK
ns
ns
ns
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz f
CK
for 400Mb/sec/pin, 267MHz f
CK
for 533Mb/sec/
pin, 333MHz f
CK
for 667Mb/sec/pin, 400MHz f
CK
for 800Mb/
sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1 , 2 , 3, 4 , 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-
strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
-PASR(Partial Array Self Refresh)
-50ohm ODT
-High Temperature Self-Refresh rate enable
• Average Refresh Period 7.8us at lower than T
CASE
85°C,
3.9us at 85°C < T
CASE
< 95
°C
• All of Lead-free products are compliant for RoHS
The 256Mb DDR2 SDRAM is organized as a 4Mbit x 16 I/Os x 4
banks device. This synchronous device achieves high speed dou-
ble-data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for
general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency -1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS/
CAS multiplexing style. For example, 256Mb(x16) device receive
13/9/2 addressing.
The 256Mb DDR2 device operates with a single 1.8V ± 0.1V
power supply and 1.8V ± 0.1V VDDQ.
The 256Mb DDR2 device is available in 84ball FBGAs(x16).
Note :
The functionality described and the timing specifications included in
this data sheet are for the DLL Enabled mode of operation.
Note :
This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “Samsung’s DDR2
SDRAM Device Operation & Timing Diagram”
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3.0 Package Pinout/Mechanical Dimension & Addressing
DDR2 SDRAM
3.1 x16 package pinout (Top View) : 84ball FBGA Package
1
VDD
DQ14
VDDQ
DQ12
VDD
DQ6
VDDQ
DQ4
VDDL
2
NC
VSSQ
DQ9
VSSQ
NC
VSSQ
DQ1
VSSQ
VREF
CKE
3
VSS
UDM
VDDQ
DQ11
VSS
LDM
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
7
VSSQ
UDQS
VDDQ
DQ10
VSSQ
LDQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
8
UDQS
VSSQ
DQ8
VSSQ
LDQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
NC
9
VDDQ
DQ15
VDDQ
DQ13
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
NC
BA0
A10/AP
VDD
VSS
A3
A7
VSS
VDD
A12
Note :
1. VDDL and VSSDL are power and ground for the DLL.
2. In case of only 8 DQs out of 16 DQs are used, LDQS, LDQSB and DQ0~7 must be used.
1
2
3
4
5
6
7
8
9
Ball Locations (x16)
: Populated Ball
+ : Depopulated Ball
A
B
C
D
E
F
Top View
(See the balls through the Package)
G
H
J
K
L
M
N
P
R
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