128Kx24 Bit High-Speed CMOS Static RAM(3.3V Operating)
Operated at Commercial and Industrial Temperature Ranges.
for AT&T
CMOS SRAM
Revision History
Rev. No.
Rev. 0.0
Rev. 0.1
Rev. 0.2
Rev. 0.3
History
Design-In Specification
Pin Configurations Modified ( page 2 )
Add Timing Diagram page 6 ~ 8 )
Modified Read Cycle Timing(2)
1) Version change from M to D
2) C
in
from 20 to 15 pF
3) Icc from 300 to 170mA for 9ns products
from 270 to 150mA for 10ns products
from 240 to 130mA for 12ns products
4) Isb ( TTL ) from 120 to 40 mA for all products
( CMOS ) from 30 to 15 mA for all products
5) Part number change from -9 to -09 for 9ns products
Change write parameter( tDW) from 6ns to 5ns at -10
Final Specification Release
Draft Data
Dec. 05. 2000
Mar. 07. 2001
April. 04.2001
June. 23.2001
Remark
Design-In
Preliminary
Preliminary
Preliminary
Rev. 0.4
Rev. 1.0
Oct. 31. 2001
Dec. 19. 2001
Preliminary
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions,
please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Revision 1.0
December 2001
K6R3024V1D
for AT&T
CMOS SRAM
128K x 24 Bit High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
• Fast Access Time 9,10,12ns
• Power Dissipation
Standby (TTL)
: 40mA(Max.)
(CMOS) : 15mA(Max.)
Operating K6R3024V1D-09 : 170mA(Max.)
K6R3024V1D-10 : 150mA(Max.)
K6R3024V1D-12 : 130mA(Max.)
Single 3.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• 119(7x17)Pin Ball Grid Array Package(14mmx22mm)
• Operating in Commercial and Industrial Temperature range.
GENERAL DESCRIPTION
The K6R3024V1D is a 3,145,728-bit high-speed Static Random
Access Memory organized as 131,072 words by 24 bits. The
K6R3024V1D uses 24 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG’
s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The K6R3024V1D is a three
megabit static RAM constructed on an multilayer laminate sub-
strate using three 3.3V, 128K x 8 static RAMS encapsulated in a
Ball Grid Array(BGA).
PIN FUNCTION
Pin Name
A
0
- A
16
WE
Pin Function
Addresses Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+3.3v)
Ground
No Connection
FUNCTIONAL BLOCK DIAGRAM
A0-16
CS1
CS2
CS3
WE
OE
17
128K x 8 128K x 8 128K x 8
SRAM
SRAM
SRAM
8
I/O
0-7
8
I/O
8-15
8
I/O
16-23
CS
1
,CS
2
,
CS
3
OE
I/O
0
~ I/O
23
V
CC
V
ss
NC
ORDERING INFORMATION
K6R3024V1D-HC09/HC10/HC12
K6R3024V1D-HI09/HI10/HI12
Commercial Temp.
Industrial Temp.
PIN CONFIGURATIONS
(TOP VIEW)
K6R3024V1D
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
2
A
A
NC
V
CC
V
ss
V
CC
V
ss
V
CC
V
ss
V
CC
V
ss
V
CC
V
ss
V
CC
NC
A
A
3
A
A
CS
2
V
ss
V
CC
V
ss
V
CC
V
ss
V
CC
V
ss
V
CC
V
ss
V
CC
V
ss
NC
A
A
4
A
CS
1
NC
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
V
ss
NC
WE
OE
5
A
A
CS
3
V
ss
V
CC
V
ss
V
CC
V
ss
V
CC
V
ss
V
CC
V
ss
V
CC
V
ss
NC
A
A
6
A
A
NC
V
CC
V
ss
V
CC
V
ss
V
CC
V
ss
V
CC
V
ss
V
CC
V
ss
V
CC
NC
A
A
7
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
-2-
Revision 1.0
December 2001
K6R3024V1D
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
d
T
STG
T
A
T
A
Rating
-0.5 to 4.6
-0.5 to 4.6
2
-65 to 150
0 to 70
-40 to 85
for AT&T
CMOS SRAM
Unit
V
V
W
°C
°C
°C
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TRUTH TABLE
CS
1
H
X
X
L
L
L
CS
2
CS
3
X
X
H
L
L
L
OE
X
X
X
L
X
H
WE
X
X
X
H
L
H
Mode
Standby
Standby
Standby
Read
Write
Outputs Disabled
I/O
High-Z
High-Z
High-Z
DATA
OUT
DATA
IN
High-Z
Power
Standby
Standby
Standby
Active
Active
Active
X
L
X
H
H
H
RECOMMENDED DC OPERATING CONDITIONS
*(T
A
=0 to 70°C)
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
IH
V
IL
Min
3.0
2.0
-0.3**
Typ
3.3
-
-
Max
3.6
V
CC
+0.3***
0.8
Unit
V
V
V
*
The above parameters are also guaranteed at industrial temperature range.
** V
IL
(Min) = -2.0V a.c(Pulse Width
≤
8ns) for I
≤
20mA.
*** V
IH
(Max) = V
CC
+ 2.0V a.c (Pulse Width
≤
8ns) for I
≤
20mA.
-3-
Revision 1.0
December 2001
K6R3024V1D
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
V
IN
=V
ss
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
Min. Cycle, CS=V
IH
-09
-10
-12
Standby Current
I
SB
-09
-10
-12
I
SB1
f=0MHz, CS
≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
-09
-10
-12
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
I
OL
=8mA
I
OH
=-4mA
Test Conditions
for AT&T
CMOS SRAM
Min
-
-
-
-
-
-
-
-
-
-
-
-
2.4
Max
6
2
170
150
130
40
40
40
15
15
15
0.4
-
Unit
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
* The above parameters are also guaranteed at industrial temperature range.
* CS represents CS
1
, CS
2
and CS
3
in this data sheet. CS
2
as of opposite polarity to CS
1
and CS
3.
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* Capacitance is sampled and not 100% tested
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
15
Unit
pF
pF
AC TEST CONDITIONS*
(T
A
=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and output Timing Reference Levels
Output Load
* The above parameters are also guaranteed at industrial temperature range.
Value
0V to 3.0V
3ns
1.5V
See Below
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
R
L
= 50Ω
V
L
= 1.5V
D
OUT
216Ω
5pF*
+3.3V
319Ω
D
OUT
Z
O
= 50Ω
30pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
-4-
Revision 1.0
December 2001
K6R3024V1D
READ CYCLE*
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power DownTime
Symbol
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
PU
t
PD
K6R3024V1D-09
Min
9
-
-
-
3
0
0
0
3
0
-
Max
-
9
9
4
-
-
4
5
-
-
9
K6R3024V1D-10
Min
10
-
-
-
3
0
0
0
3
0
-
Max
-
10
10
5
-
-
5
6
-
-
10
for AT&T
CMOS SRAM
K6R3024V1D-12
Min
12
-
-
-
3
0
0
0
3
0
-
Max
-
12
12
6
-
-
6
7
-
-
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE*
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WP1
t
WR
t
WHZ
t
DW
t
DH
t
OW
K6R3024V1D-09
Min
9
7
0
7
7
9
0
0
5
0
3
Max
-
-
-
-
-
-
-
5
-
-
-
K6R3024V1D-10
Min
10
7
0
7
7
9
0
0
5
0
3
Max
-
-
-
-
-
-
-
5
-
-
-
K6R3024V1D-12
Min
12
8
0
8
8
10
0
0
7
0
3
Max
-
-
-
-
-
-
-
5
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* This parameter is guaranteed by design but not tested.
These specifications are for the individual K6R3024V1D Static RAMs.
