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SGRAM MODULE

KMM965G511AQ(P)N / KMM966G511AQ(P)N

4MB SGRAM MODULE

(512Kx64 SODIMM based on 512Kx32 SGRAM)

Unbuffered SGRAM

Graphics

64-bit Non-ECC/Parity

144-pin SODIMM

Revision 0.0

July 1999

-1-

Rev. 0.0 (Jul. 1999)

SGRAM MODULE

Revision History

Revision 0.0 (July 1999)

• First edition

KMM965G511AQ(P)N / KMM966G511AQ(P)N

-2-

Rev. 0.0 (Jul. 1999)

SGRAM MODULE

KMM965G511AQ(P)N / KMM966G511AQ(P)N

KMM965G511AQ(P)N / KMM966G511AQ(P)N SGRAM SODIMM

512Kx64 SGRAM SODIMM based on 512Kx32, 2K Refresh, 3.3V Synchronous Graphic RAMs

GENERAL DESCRIPTION

The Samsung KMM965(6)G511AQ(P)N is a 512K bit x 64

Synchronous Graphic RAM high density memory module. The

Samsung KMM965(6)G511AQ(P)N consists of two CMOS

512K x 32 bit Synchronous Graphic RAMs in 100pin QFP

packages mounted on a 144pin glass-epoxy substrate. Five

0.1uF decoupling capacitors are mounted on the printed

circuit

board

for

each

Synchronous

GRAM.

The

KMM965(6)G511AQ(P)N is a Small Outline Dual In-line Mem-

ory Module and is intended for mounting into 144-pin edge

connector sockets.

Synchronous design allows precise cycle control with the use

of system clock. I/O transactions are possible on every clock

cycle. Range of operating frequencies, programmable laten-

cies and burst lengths allows the same device to be useful for a

variety of high bandwidth, high performance memory system

•

FEATURE

• Performance range

Part NO.

KMM965G511AQ(P)N-G5

KMM965G511AQ(P)N-G6

KMM965G511AQ(P)N-G7

KMM965G511AQ(P)N-G8

Max. Freq. (t

)

200MHz (5ns) @CL=3

166MHz (6ns) @CL=3

143MHz (7ns) @CL=3

125MHz (8ns) @CL=3

* KM965G511AQN : based on PQFP Component

KM965G511APN : based on TQFP Component

Burst Mode Operation

BLOCK-WRITE and Write-per-bit capability

Independent byte operation via DQM0 ~ 7

Auto & Self Refresh Capability (2048 cycles / 32ms)

LVTTL compatible inputs and outputs

Single 3.3V±0.3V power supply

MRS cycle with address key programs.

CAS Latency (2, 3)

Burst Length (1, 2, 4, 8 & Full page)

Data Scramble (Sequential & Interleave)

• Optional Serial PD with EEPROM (KMM966G511A)

• Resistor Strapping Options for speed and CAS Latency

• PCB : Height(1000mil), single sided components

PIN CONFIGURATIONS (Front Side / Back Side)

Front

DQ63

DQ61

DQ59

DQ57

DQ55

DQ53

DQ51

DQ49

DQM7

DQM5

DQ47

DQ45

DQ43

DQ41

DQ39

DQ37

DQ35

DQ33

RSVD

Back

DQ62

DQ60

DQ58

DQ56

DQ54

DQ52

DQ50

DQ48

DQM6

DQM4

DQ46

DQ44

DQ42

DQ40

DQ38

DQ36

DQ34

DQ32

RSVD

Front

Back

101

103

105

107

109

111

113

115

117

119

121

123

125

127

129

131

133

135

137

139

141

143

Front

DQ31

DQ29

DQ27

DQ25

DQ23

DQ21

DQ19

DQ17

DQM3

DQM1

DQ15

DQ13

DQ11

DQ9

DQ7

DQ5

DQ3

DQ1

**SDA

Back

PIN NAMES

Pin Name

A0 ~ A9

BA(A10)

DQ0 ~ 63

CKE

CS0, *CS1

RAS

CAS

DSF

DQM0 ~ 7

**SDA

**SBA

**SCL

RSVD

RFU

Function

Address Input(multiplexed)

Bank Select Address

Data Input / Output

Clock Enable Input

Chip Select Input

Row Address Strobe

Column Address Strobe

Write Enable

Define Special Function

DQM

Power Supply (3.3V)

Ground

Serial Address Data I/O

EEPROM Device Address

Serial Clock

Reserved

Reserved for future use

No Connection

96 DQ30

98 DQ28

100 DQ26

102 DQ24

104

106 DQ22

108 DQ20

110 DQ18

112 DQ16

114

116 DQM2

118 DQM0

120

122 DQ14

124 DQ12

126 DQ10

128 DQ8

130

132 DQ6

134 DQ4

136 DQ2

138 DQ0

140

142 **SCL

144

Voltage Key

RSVD

DSF

RFU

CS1

RAS

CLK1

RSVD

(A11)

BA(A10)

RSVD

RFU

**SBA

CS0

CAS

CKE

CLK0

RSVD

A9/AP

CLK0, *CLK1 Clock Input

These pins are not used in this module.

These pins should be NC in the system

which does not support SPD.

SAMSUNG ELECTRONICS CO. Ltd. reserves the right to change products and specifications without notice.

-3-

Rev. 0.0 (Jul. 1999)

SGRAM MODULE

CLK

Name

System Clock

Chip Select

KMM965G511AQ(P)N / KMM966G511AQ(P)N

Input Function

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one clock + t

prior to new command.

Disable input buffers for power down in standby.

Row / column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA9, column address : CA0 ~ CA7

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

Data inputs/outputs are multiplexed on the same pins.

Enables write per bit, block write and special mode register set.

Power and ground for the input buffers and the core logic.

PIN CONFIGURATION DESCRIPTION

CKE

Clock Enable

A0 ~ A9

BA(A10)

RAS

CAS

DQM0 ~ 7

DQ0 ~ 63

DSF

Address

Bank Select Address

Row Address Strobe

Column Address Strobe

Write Enable

Data Input/Output Mask

Data Input/Output

Define Special Function

Power Supply/Ground

RESISTOR STRAPPING OPTIONS

Three resistor straps are used to indicate the synchronous clock frequency (period) and memory timing.Timing information

for each clock frequency is indicated in the section titled

AC CHARATERISTICS.

Clock Frequency and Memory Timing

Cycle Time

8ns

7ns

6ns

5ns

DQ30

DQ29

CAS Latency

2 and 3

DQ31

-4-

Rev. 0.0 (Jul. 1999)

SGRAM MODULE

FUNCTIONAL BLOCK DIAGRAM

KMM965G511AQ(P)N / KMM966G511AQ(P)N

CS0

•

DQM0

DQ0

•

DQ7

DQM1

DQ8

DQM0

DQ0

•

DQ7

DQM1

DQ8

•

DQ15

DQM2

DQ16

•

DQ23

DQM3

DQ24

•

DQ31

DQM4

DQ32

DQ39

DQM5

DQ40

•

DQM0

DQ0

•

DQ7

DQM1

DQ8

•

DQ15

DQM2

DQ16

•

DQ23

DQM3

DQ24

•

DQ31

•

DQ15

DQM2

DQ16

DQ47

DQM6

DQ48

•

DQ23

DQM3

DQ24

DQ55

DQM7

DQ56

•

DQ31

•

DQ63

•

CKE

RAS

CAS

DSF

A(9:0)

BA(A10)

U0 to U1

0Ω

CLK0

U0, U1

Serial PD

SCL

Vss

•

Five 0.1uF Capacitors

per SGRAM device

To all SGRAMs

SBA

•

SDA

•

* Serial PD is optional

-5-

Rev. 0.0 (Jul. 1999)

参数对比

与KMM965G511APN-G7相近的元器件有：KMM965G511AQN-G6、KMM965G511APN-G5、KMM965G511APN-G8、KMM965G511AQN-G7、KMM965G511APN-G6、KMM965G511AQN-G5、KMM965G511AQN-G8。描述及对比如下：

型号	KMM965G511APN-G7	KMM965G511AQN-G6	KMM965G511APN-G5	KMM965G511APN-G8	KMM965G511AQN-G7	KMM965G511APN-G6	KMM965G511AQN-G5	KMM965G511AQN-G8
描述	Synchronous Graphics RAM Module, 512KX64, 5.5ns, CMOS, SODIMM-144	Synchronous Graphics RAM Module, 512KX64, 5.5ns, CMOS, SODIMM-144	Synchronous Graphics RAM Module, 512KX64, 4.5ns, CMOS, SODIMM-144	Synchronous Graphics RAM Module, 512KX64, 6ns, CMOS, SODIMM-144	Synchronous Graphics RAM Module, 512KX64, 5.5ns, CMOS, SODIMM-144	Synchronous Graphics RAM Module, 512KX64, 5.5ns, CMOS, SODIMM-144	Synchronous Graphics RAM Module, 512KX64, 4.5ns, CMOS, SODIMM-144	Synchronous Graphics RAM Module, 512KX64, 6ns, CMOS, SODIMM-144
零件包装代码	SODIMM	SODIMM	SODIMM	SODIMM	SODIMM	SODIMM	SODIMM	SODIMM
包装说明	DIMM, DIMM144,32	DIMM, DIMM144,32	DIMM, DIMM144,32	DIMM, DIMM144,32	DIMM, DIMM144,32	DIMM, DIMM144,32	DIMM, DIMM144,32	DIMM, DIMM144,32
针数	144	144	144	144	144	144	144	144
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
最长访问时间	5.5 ns	5.5 ns	4.5 ns	6 ns	5.5 ns	5.5 ns	4.5 ns	6 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	143 MHz	166 MHz	200 MHz	125 MHz	143 MHz	166 MHz	200 MHz	125 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-XZMA-N144	R-XZMA-N144	R-XZMA-N144	R-XZMA-N144	R-XZMA-N144	R-XZMA-N144	R-XZMA-N144	R-XZMA-N144
内存密度	33554432 bit	33554432 bit	33554432 bit	33554432 bit	33554432 bit	33554432 bit	33554432 bit	33554432 bit
内存集成电路类型	SYNCHRONOUS GRAPHICS RAM MODULE	SYNCHRONOUS GRAPHICS RAM MODULE	SYNCHRONOUS GRAPHICS RAM MODULE	SYNCHRONOUS GRAPHICS RAM MODULE	SYNCHRONOUS GRAPHICS RAM MODULE	SYNCHRONOUS GRAPHICS RAM MODULE	SYNCHRONOUS GRAPHICS RAM MODULE	SYNCHRONOUS GRAPHICS RAM MODULE
内存宽度	64	64	64	64	64	64	64	64
功能数量	1	1	1	1	1	1	1	1
端口数量	1	1	1	1	1	1	1	1
端子数量	144	144	144	144	144	144	144	144
字数	524288 words	524288 words	524288 words	524288 words	524288 words	524288 words	524288 words	524288 words
字数代码	512000	512000	512000	512000	512000	512000	512000	512000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	512KX64	512KX64	512KX64	512KX64	512KX64	512KX64	512KX64	512KX64
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
封装代码	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
封装等效代码	DIMM144,32	DIMM144,32	DIMM144,32	DIMM144,32	DIMM144,32	DIMM144,32	DIMM144,32	DIMM144,32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
电源	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	2048	2048	2048	2048	2048	2048	2048	2048
自我刷新	YES	YES	YES	YES	YES	YES	YES	YES
最大待机电流	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A	0.004 A
最大压摆率	0.46 mA	0.52 mA	0.54 mA	0.4 mA	0.46 mA	0.52 mA	0.54 mA	0.4 mA
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	NO	NO	NO	NO	NO	NO	NO	NO
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子形式	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
端子节距	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	ZIG-ZAG	ZIG-ZAG	ZIG-ZAG	ZIG-ZAG	ZIG-ZAG	ZIG-ZAG	ZIG-ZAG	ZIG-ZAG
厂商名称	SAMSUNG(三星)	-	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)	SAMSUNG(三星)