KS8995MA/FQ
Integrated 5-Port 10/100 Managed Switch
Rev 2.9
General Description
The KS8995MA/FQ is a highly integrated Layer 2
managed switch with optimized bill of materials (BOM)
cost for low port count, cost-sensitive 10/100Mbps
switch systems with both copper and optic fiber media.
It also provides an extensive feature set such as
tag/port-based VLAN, quality of service (QoS) priority,
management, MIB counters, dual MII interfaces and
CPU control/data interfaces to effectively address both
current and emerging fast Ethernet applications.
The KS8995MA/FQ contains five 10/100 transceivers
with patented mixed-signal low-power technology, five
media access control (MAC) units, a high-speed non-
blocking switch fabric, a dedicated address lookup
engine, and an on-chip frame buffer memory.
All PHY units support 10BASE-T and 100BASE-TX.
In addition, two of the PHY units support 100BASE-FX
(KS8995MA is ports 4 and 5, KS8995FQ is port 3 and
port 4).
Functional Diagram
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
September 2008
M9999-091508
Micrel, Inc.
KS8995MA/FQ
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
MII-P5
MDC, MDI/O
MII- SW or SNI
Control Reg I/F
LED0[5:1]
LED1[5:1]
LED2[5:1]
10/100
T/Tx 1
10/100
T/Tx 2
10/100
T/Tx/Fx 3
10/100
T/Tx/Fx 4
10/100
T/Tx 5
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100
MAC 5
SNI
SPI
1K Look Up
Engine
FIFO, Flow Control, VLAN
Tagging, Priority
Queue
Mgmnt
Buffer
Mgmnt
Frame
Buffers
MIB
Counters
EEPROM
I/F
LED I/F
Control
Registers
KSZ8995FQ
Notes:
1. KS8995MA has either TX copper or FX fiber for port 4 and port 5, other ports are the TX copper only.
2. KS8995FQ has either TX copper or FX fiber for port 3 and port 4, other ports are the TX copper only.
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KS8995MA/FQ
•
Per-port based software power-save on PHY (idle
link detection, register configuration preserved)
•
QoS/CoS packets prioritization supports: per port,
802.1p and DiffServ based
•
802.1p/q tag insertion or removal on a per-port basis
(egress)
•
MDC and MDI/O interface support to access the MII
PHY control registers (not all control registers)
•
MII local loopback support
•
On-chip 64Kbyte memory for frame buffering (not
shared with 1K unicast address table)
•
Wire-speed reception and transmission
•
Integrated look-up engine with dedicated 1K MAC
addresses
•
Full duplex IEEE 802.3x and half-duplex back
pressure flow control
•
Comprehensive LED support
•
7-wire SNI support for legacy MAC interface
•
Automatic MDI/MDI-X crossover for plug-and-play
•
Disable automatic MDI/MDI-X option
•
Low power:
Core: 1.8V
Digital I/O: 3.3V
Analog I/O: 2.5V or 3.3V
•
0.18µm CMOS technology
•
Commercial temperature range: 0°C to +70°C
•
Industrial temperature range: –40°C to +85°C
•
Available in 128-pin PQFP package
Features
•
Integrated switch with five MACs and five fast
Ethernet transceivers fully compliant to IEEE 802.3u
standard
•
Shared memory based switch fabric with fully non-
blocking configuration
•
1.4Gbps high-performance memory bandwidth
•
10BASE-T, 100BASE-TX, and 100BASE-FX modes
•
Dual MII configuration: MII-Switch (MAC or PHY
mode MII) and MII-P5 (PHY mode MII)
•
IEEE 802.1q tag-based VLAN (16 VLANs, full-range
VID) for DMZ port, WAN/LAN separation or inter-
VLAN switch links
•
VLAN ID tag/untag options, per-port basis
•
Programmable rate limiting 0Mbps to 100Mbps,
ingress and egress port, rate options for high and low
priority, per-port basis in 32Kbps increments
•
Flow control or drop packet rate limiting (ingress port)
•
Integrated MIB counters for fully compliant statistics
gathering, 34 MIB counters per port
•
Enable/Disable option for huge frame size up to 1916
bytes per frame
•
IGMP v1/v2 snooping for multicast packet filtering
•
Special tagging mode to send CPU info on ingress
packet’s port value
•
SPI slave (complete) and MDIO (MII PHY only) serial
management interface for control of register
configuration
•
MAC-id based security lock option
•
Control registers configurable on-the-fly (port-priority,
802.1p/d/q, AN...)
•
CPU read access to MAC forwarding table entries
•
802.1d Spanning Tree Protocol
•
Port mirroring/monitoring/sniffing: ingress and/or
egress traffic to any port or MII
•
Broadcast storm protection with % control – global
and per-port basis
•
Optimization for fiber-to-copper media conversion
•
Full-chip hardware power-down support (register
configuration not saved)
Applications
•
•
•
•
•
•
•
•
•
Broadband gateway/firewall/VPN
Integrated DSL or cable modem multi-port router
Wireless LAN access point plus gateway
Home networking expansion
Standalone 10/100 switch
Hotel/campus/MxU gateway
Enterprise VoIP gateway/phone
FTTx customer premise equipment
Managed Media converter
Ordering Information
Part Number
Standard
KS8995MA
KS8995FQ
KS8995MAI
KS8995FQI
Pb-Free
KSZ8995MA
KSZ8995FQ
KSZ8995MAI
KSZ8995FQI
Temperature
Range
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
Package
128-Pin PQFP
128-Pin PQFP
128-Pin PQFP
128-Pin PQFP
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KS8995MA/FQ
Revision History
Revision
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Date
10/10/03
10/30/03
4/01/04
1/19/05
4/13/05
2/6/06
7/12/06
6/01/07
03/20/08
09/15/08
Summary of Changes
Created.
Editorial changes on electrical characteristics.
Editorial changes on the TTL input and output electrical characteristics.
Insert recommended reset circuit, pg. 70. Editorial, Pg. 36.
Changed VDDIO to 3.3V.
Changed Jitter to 16 ns Max.
Added Pb-Free option for Industrial version.
Add a note for VLAN table write, improve the timing diagram for MII interface, update pin
description for PCRS, PCOL, etc. And update the description of the register bits for the
loopback, etc.
Add the package thermal information in the operating rating and the transformer power
consumption information in the electrical characteristics note.
Add KSZ8995FQ information and pin description.
Add KSZ8995FQ block diagram and descriptions for revision ID and LED mode.
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KS8995MA/FQ
Contents
System Level Applications........................................................................................................................................... 8
Pin Configuration ........................................................................................................................................................ 10
Pin Description (by Number)...................................................................................................................................... 11
Pin Description (by Name) ......................................................................................................................................... 17
Introduction ................................................................................................................................................................. 23
Functional Overview: Physical Layer Transceiver .................................................................................................. 23
100BASE-TX Transmit.............................................................................................................................................. 23
100BASE-TX Receive............................................................................................................................................... 23
PLL Clock Synthesizer.............................................................................................................................................. 23
Scrambler/De-Scrambler (100BASE-TX only).......................................................................................................... 24
100BASE-FX Operation............................................................................................................................................ 24
100BASE-FX Signal Detection ................................................................................................................................. 24
100BASE-FX far End fault ........................................................................................................................................ 24
10BASE-T Transmit .................................................................................................................................................. 24
10BASE-T Receive ................................................................................................................................................... 24
Power Management.................................................................................................................................................. 24
MDI/MDI-X Auto Crossover ...................................................................................................................................... 24
Auto-Negotiation ....................................................................................................................................................... 24
Functional Overview: Switch Core ............................................................................................................................ 25
Address Look-Up ...................................................................................................................................................... 25
Learning .................................................................................................................................................................... 25
Migration ................................................................................................................................................................... 25
Aging ......................................................................................................................................................................... 25
Forwarding ................................................................................................................................................................ 25
Switching Engine ...................................................................................................................................................... 26
Media Access Controller (MAC) Operation............................................................................................................... 26
Inter-Packet Gap (IPG)
............................................................................................................................................. 26
Backoff Algorithm......................................................................................................................................................
26
Late Collision
............................................................................................................................................................ 26
Illegal Frames
........................................................................................................................................................... 26
Flow Control..............................................................................................................................................................
26
Half-Duplex Back Pressure
........................................................................................................................... 28
Broadcast Storm Protection
...................................................................................................................................... 28
MII Interface Operation ............................................................................................................................................. 29
SNI Interface Operation ............................................................................................................................................ 31
Advanced Functionality.............................................................................................................................................. 31
Spanning Tree Support............................................................................................................................................. 31
Special Tagging Mode .............................................................................................................................................. 32
IGMP Support ........................................................................................................................................................... 33
Port Mirroring Support............................................................................................................................................... 34
VLAN Support ........................................................................................................................................................... 34
Rate Limit Support .................................................................................................................................................... 35
Configuration Interface.............................................................................................................................................. 36
I
2
C Master Serial Bus Configuration
......................................................................................................................... 38
SPI Slave Serial Bus Configuration
.......................................................................................................................... 38
MII Management Interface (MIIM) ............................................................................................................................ 41
Register Description ................................................................................................................................................... 42
Global Registers ....................................................................................................................................................... 43
Register 0 (0x00): Chip ID0
...................................................................................................................................... 43
Register 1 (0x01): Chip ID1 / Start Switch
................................................................................................................ 43
Register 2 (0x02): Global Control 0
.......................................................................................................................... 43
Register 3 (0x03): Global Control 1
.......................................................................................................................... 43
Register 4 (0x04): Global Control 2
.......................................................................................................................... 44
Register 5 (0x05): Global Control 3
.......................................................................................................................... 45
Semptember 2008
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stm32/stm8
