L6918 L6918A
5 BIT PROGRAMMABLE MULTIPHASE CONTROLLER
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OUTPUT CURRENT IN EXCESS OF 100A
ULTRA FAST LOAD TRANSIENT RESPONSE
REMOTE SENSE BUFFER
INTEGRATED 2A GATE DRIVERS
5 BIT VID VOLTAGE POSITIONING, VRM 9.0
0.6% INTERNAL REFERENCE ACCURACY
DIGITAL 2048 STEP SOFT-START
OVP & OCP PROTECTIONS
Rdson or Rsense CURRENT SENSING
1200KHz EFFECTIVE SWITCHING
FREQUENCY, EXTERNALLY ADJUSTABLE
POWER GOOD OUTPUT AND INHIBIT
PACKAGE: SO28
DESCRIPTION
L6918A is a master device that it has to be combined
with the L6918,slave, realizing a 4-phases topology,
interleaved. The device kit is specifically designed to
provide a high performance/high density DC/DC con-
version for high current microprocessors and distrib-
uted power. Each device implements a dual-phase
step-down controller with a 180° phase-shift between
each phase.
A precise 5-bit DAC allows adjusting the output volt-
age from 1.100V to 1.850V with 25mV binary steps.
The high peak current gate drives affords to have
high system switching frequency, typically of
1200KHz, and higher by external adjustement.
The device kit assure a fast protection against OVP,
UVP and OCP. An internal crowbar, by turning on the
low side mosfets, eliminates the need of external pro-
tection. In case of over-current, the system works in
Constant Current mode.
SO28
ORDERING NUMBERS: L6918D, L6918AD
L6918DTR, L6918ADTR
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APPLICATIONS
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HIGH DENSITY DC-DC FOR SERVERS AND
WORKSTATIONS
SUPPLY FOR HIGH CURRENT
MICROPROCESSORS
DISTRIBUTED POWER
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PIN CONNECTIONS
LGATE1
VCCDR
PHASE1
UGATE1
BOOT1
VCC
SGND
COMP
FB
VPROG_OUT
SYNC_OUT
SLAVE_OK
ISEN1
PGNDS1
1
2
3
4
5
28
27
26
25
24
PGND
LGATE2
PHASE2
UGATE2
BOOT2
PGOOD
VID4
VID3
VID2
VID1
VID0
OSC / INH / FAULT
ISEN2
PGNDS2
LGATE1
VCCDR
PHASE1
UGATE1
BOOT1
VCC
SGND
COMP
FB
VSEN
FBR
FBG
ISEN1
PGNDS1
1
2
3
4
5
6
28
27
26
25
24
23
PGND
LGATE2
PHASE2
UGATE2
BOOT2
PGOOD
VPROG_IN
SYNC_IN
SLAVE_OK
SYNC / ADJ
SYNC_OUT
OSC / INH / FAULT
ISEN2
PGNDS2
L6918A
(
Master)
6
7
8
9
10
11
12
13
14
23
22
21
20
19
18
17
16
15
L6918
7
8
9
10
11
12
13
14
(Slave)
22
21
20
19
18
17
16
15
October 2002
1/35
L6918 L6918A
L6918A (MASTER) DEVICE BLOCK DIAGRAM
SYNC_ OUT
ROSC / INH
SGND
VCCDR
BOOT1
2 PHASE
OSCILLATOR
LOGIC PWM
ADAPTIVE ANTI
CROSS CONDUCTION
HS
UGATE1
PHASE1
SLAVE_OK
SYNCH.
CIRCUITRY
P WM1
CU RREN T
COR RECTIO N
LOGIC AND
PROTECTIONS
CH1
OCP
LS
LGATE1
ISEN1
VCC
VCC DR
TO TAL
CUR RENT
CURR ENT
A VG
PGOOD
CURRENT
READING
CURRENT
READING
CU RREN T
COR RECTIO N
PGNDS1
PGND
PGNDS2
ISEN2
CH2 OCP
CH1 OCP
DIGITAL
SOFT- STAR T
CH2
OCP
I
FB
LOGIC PWM
A DAPTIVE ANTI
CROSS CONDUCTION
LS
LGATE2
VID4
VID3
VID2
VID1
VID0
PHASE2
HS
UGATE2
BOOT2
P WM2
DAC
ERROR
AMPLIFIER
Vc c
VSEN
FB
COMP
Vcc
L6918 (SLAVE) DEVICE BLOCK DIAGRAM
SLAVE / ADJ
SYNC_OUT
ROSC / INH
SGND
VCCDR
BOOT1
SYNC_I N
SYNCH.
CIRCUITRY
SLAVE_OK
2 PHASE
OSCILLATOR
P WM1
LOGIC PWM
ADAPTIVE ANT I
CROSS CONDUCTION
HS
UGATE1
PHASE1
CU RREN T
COR RECTIO N
LOGIC AND
PROTECTIONS
CH1
OCP
LS
LGATE1
ISEN1
VCC
VCC DR
TO TAL
CUR RENT
CURR ENT
A VG
PGOOD
CURRENT
READING
CURRENT
READING
CU RREN T
COR RECTIO N
PGNDS1
PGND
PGNDS2
ISEN2
CH2 OCP
CH1 OCP
1 0k
CH2
OCP
FBG
FBR
10 k
10 k
I
FB
LOGIC PWM
A DAPTIVE AN TI
CROSS CONDUCTION
VPROG_IN
LS
LGATE2
PHASE2
HS
UGATE2
BOOT2
P WM2
1 0k
REMOTE
BUFFER
ERROR
AMPLIFIER
V SEN
VSEN
Vc c
FB
COMP
Vcc
2/35
L6918 L6918A
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc, V
CCDR
V
BOOT
-V
PHASE
V
UGATE1
-V
PHASE1
V
UGATE2
-V
PHASE2
LGATE1, PHASE1, LGATE2, PHASE2 to PGND
VID0 to VID4
All other pins to PGND
V
PHASEx
Sustainable Peak Voltage t<20nS @ 600kHz
To PGND
Boot Voltage
Parameter
Value
15
15
15
-0.3 to Vcc+0.3
-0.3 to 5
-0.3 to 7
26
Unit
V
V
V
V
V
V
V
THERMAL DATA
Symbol
R
th j-amb
T
max
T
storage
T
j
P
MAX
Parameter
Thermal Resistance Junction to Ambient
Maximum junction temperature
Storage temperature range
Junction Temperature Range
Max power dissipation at Tamb=25°C
Value
60
150
-40 to 150
0 to 125
2
Unit
°C
/ W
°C
°C
°C
W
L6918A (MASTER) PIN FUNCTION
N.
1
2
3
4
5
6
7
8
9
Name
LGATE1
VCCDR
PHASE1
UGATE1
BOOT1
VCC
GND
COMP
Channel 1 low side gate driver output.
LS Mosfet driver supply. 5V or 12V buses can be used.
This pin is connected to the Source of the upper mosfet and provides the return path for the
high side driver of channel 1.
Channel 1 high side gate driver output.
Channel 1 bootstrap capacitor pin. This pin supplies the high side driver. Connect through a
capacitor to the PHASE1 pin and through a diode to Vcc (cathode vs. boot).
Device supply voltage. The operative supply voltage is 12V.
All the internal references are referred to this pin. Connect it to the PCB signal ground.
Description
10
This pin is connected to the error amplifier output and is used to compensate the control
feedback loop.
FB
This pin is connected to the error amplifier inverting input and is used to compensate the
voltage control feedback loop.
A current proportional to the sum of the current sensed in both channel is sourced from this pin
(50µA at full load, 70µA at the Over Current threshold). Connecting a resistor R
FB
between
this pin and VSEN pin allows programming the droop effect.
VPROG_OUT Reference voltage output used for voltage regulation.
This pin must be connected together with the slave device VPROG_IN pin.
Filter to SGND with 1nF capacitor (a total 30nF distributed capacitance is allowed).
SYNC_OUT
Synchronization output signal. From this pin exits a square - 50% duty cycle - 5Vpp –90 deg
phase shifted wave clock signal that the Slave device PLL locks to.
Connect this pin to the Slave SYNC_IN pin.
Open-drain input/output used for start-up and to manage protections as shown in the timing
diagram. Internally pulled-up. Connect together with other IC’s SLAVE_OK pin. Filter with 1nF
capacitor vs. SGND.
11
12
SLAVE_OK
3/35
L6918 L6918A
L6918A (MASTER) PIN FUNCTION
(continued)
N.
13
Name
ISEN1
Description
Channel 1 current sense pin. The output current may be sensed across a sense resistor or
across the low-side mosfet RdsON. This pin has to be connected to the low-side mosfet drain
or to the sense resistor through a resistor Rg in order to program the current intervention for
each phase at 140% as follow:
35µA
⋅
R
g
I
O CPx
= --------------------------
R
s ens e
Where 35µA is the current offset information relative to the Over Current condition (offset at
OC threshold minus offset at zero load).The net connecting the pin to the sense point must be
routed as close as possible to the PGNDS1 net in order to couple in common mode any
picked-up noise.
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15
PGNDS1
PGNDS2
Channel 1 Power Ground sense pin. The net connecting the pin to the sense point must be routed as
close as possible to the ISEN1 net in order to couple in common mode any picked-up noise.
Channel 2 Power Ground sense pin. The net connecting the pin to the sense point must be
routed as close as possible to the ISEN2 net in order to couple in common mode any picked-
up noise.
Channel 2 current sense pin. The output current may be sensed across a sense resistor or
across the low-side mosfet Rds
ON.
This pin has to be connected to the low-side mosfet drain
or to the sense resistor through a resistor Rg in order to program the current intervention for
each phase at 140% as follow:
35µA
⋅
R
g
I
O CPx
= --------------------------
R
s ens e
Where 35µA is the current offset information relative to the Over Current condition (offset at
OC threshold minus offset at zero load).
The net connecting the pin to the sense point must be routed as close as possible to the
PGNDS2 net in order to couple in common mode any picked-up noise.
Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the
external frequency is increased according to the equation:
f
S
14.82
⋅
10
=
300KHz
+ -----------------------------
R
O SC
(
KΩ
)
6
16
ISEN2
17
OSC/INH
FAULT
Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according
to the equation:
12.91
⋅
10
f
S
=
300KHz
+ -----------------------------
R
O SC
(
KΩ
)
If the pin is not connected, the switching frequency is 300KHz.
Forcing the pin to a voltage lower than 0.8V, the device stop operation and enter the inhibit
state; all mosfets are turned OFF.
18
to
22
23
VID0-4
Voltage Identification pins. These input are internally pulled-up and TTL compatible. They are
used to program the output voltage as specified in Table 1 and to set the over voltage and
power good thresholds.
Connect to GND to program a ‘0’ while leave floating to program a ‘1’.
This pin is an open collector output and is pulled low if the output voltage is not within the
above specified thresholds. It must be connected with the Slave’s PGOOD pin.
If not used may be left floating.
Channel 2 bootstrap capacitor pin. This pin supplies the high side driver. Connect through a
capacitor to the PHASE2 pin and through a diode to Vcc (cathode vs. boot).
Channel 2 high side gate driver output.
This pin is connected to the source of the upper mosfet and provides the return path for the
high side driver of channel 2.
Channel 2 low side gate driver output.
Power ground pin. This pin is common to both sections and it must be connected through the closest
path to the low side mosfets source pins in order to reduce the noise injection into the device.
7
PGOOD
24
25
26
27
28
BOOT2
UGATE2
PHASE2
LGATE2
PGND
4/35
L6918 L6918A
L6918 (SLAVE) PIN FUNCTION
N.
1
2
3
4
5
6
7
8
9
Name
LGATE1
VCCDR
PHASE1
UGATE1
BOOT1
VCC
GND
COMP
FB
Channel 1 low side gate driver output.
LS Mosfet driver supply. 5V or 12V buses can be used.
This pin is connected to the Source of the upper mosfet and provides the return path for the
high side driver of channel 1.
Channel 1 high side gate driver output.
Channel 1 bootstrap capacitor pin. This pin supplies the high side driver. Connect through a
capacitor to the PHASE1 pin and through a diode to Vcc (cathode vs. boot).
Device supply voltage. The operative supply voltage is 12V.
All the internal references are referred to this pin. Connect it to the PCB signal ground.
This pin is connected to the error amplifier output and is used to compensate the control
feedback loop.
This pin is connected to the error amplifier inverting input and is used to compensate the
voltage control feedback loop.
A current proportional to the sum of the current sensed in both channel is sourced from this pin
(50µA at full load, 70µA at the Over Current threshold). Connecting a resistor R
FB
between this
pin and VSEN pin allows programming the droop effect.
Connected to the output voltage it is able to manage Over & Under-voltage conditions and the
PGOOD signal. It is internally connected with the output of the Remote Sense Buffer for
Remote Sense of the regulated voltage.
If no Remote Sense is implemented, connect it directly to the regulated voltage in order to
manage OVP, UVP and PGOOD.
Remote sense buffer non-inverting input. It has to be connected to the positive side of the load
to perform a remote sense.
If no remote sense is implemented, connect directly to the output voltage (in this case connect
also the VSEN pin directly to the output regulated voltage).
Remote sense buffer inverting input. It has to be connected to the negative side of the load to
perform a remote sense.
Pull-down to ground if no remote sense is implemented.
Channel 1 current sense pin. The output current may be sensed across a sense resistor or
across the low-side mosfet Rds
ON.
This pin has to be connected to the low-side mosfet drain or
to the sense resistor through a resistor Rg in order to program the current intervention for each
phase at 140% as follow:
35µA
⋅
R
g
I
O CPx
= --------------------------
R
s ens e
Description
10
VSEN
11
FBR
12
FBG
13
ISEN1
Where 35µA is the current offset information relative to the Over Current condition (offset at
OC threshold minus offset at zero load).
The net connecting the pin to the sense point must be routed as close as possible to the
PGNDS1 net in order to couple in common mode any picked-up noise.
14
PGNDS1
Channel 1 Power Ground sense pin. The net connecting the pin to the sense point must be
routed as close as possible to the ISEN1 net in order to couple in common mode any picked-up
noise.
Channel 2 Power Ground sense pin. The net connecting the pin to the sense point must be
routed as close as possible to the ISEN2 net in order to couple in common mode any picked-up
noise.
15
PGNDS2
5/35
模拟与混合信号
