ECP5™ Family Data Sheet
Preliminary DS1044 Version 1.3, August 2015
ECP5 Family Data Sheet
Introduction
August 2015
Preliminary Data Sheet DS1044
Features
Higher Logic Density for Increased System
Integration
• 24K to 84K LUTs
• 197 to 365 user programmable I/Os
Programmable sysI/O™ Buffer Supports
Wide Range of Interfaces
•
•
•
•
•
•
On-chip termination
LVTTL and LVCMOS 33/25/18/15/12
SSTL 18/15 I, II
HSUL12
LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS
subLVDS and SLVS, MIPI D-PHY input inter-
faces
Shared bank for configuration I/Os
SPI boot flash interface
Dual-boot images supported
Slave SPI
TransFR™ I/O for simple field updates
Embedded SERDES
• 270 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit
SERDES, and 8-bit SERDES modes
• Data Rates 270 Mbps to 3.2 Gbps per channel
for all other protocols
• Up to four channels per device: PCI Express,
Ethernet (1GbE, SGMII, XAUI), and CPRI.
Flexible Device Configuration
•
•
•
•
•
sysDSP™
• Fully cascadable slice architecture
• 12 to 160 slices for high performance multiply
and accumulate
• Powerful 54-bit ALU operations
• Time Division Multiplexing MAC Sharing
• Rounding and truncation
• Each slice supports
— Half 36 x 36, two 18 x 18 or four 9 x 9 multipliers
— Advanced 18 x 36 MAC and 18 x 18 Multiply-
Multiply-Accumulate (MMAC) operations
Single Event Upset (SEU) Mitigation
Support
• Soft Error Detect – Embedded hard macro
• Soft Error Correction – Without stopping user
operation
• Soft Error Injection – Emulate SEU event to
debug system error handling
Flexible Memory Resources
• Up to 3.744 Mbits sysMEM™ Embedded Block
RAM (EBR)
• 194K to 669K bits distributed RAM
System Level Support
• IEEE 1149.1 and IEEE 1532 compliant
• Reveal Logic Analyzer
• On-chip oscillator for initialization and general
use
• 1.1 V core power supply
sysCLOCK Analog PLLs and DLLs
• Four DLLs and four PLLs in LFE5-45 and LFE5-
85; two DLLs and two PLLs in LFE5-25
Pre-Engineered Source Synchronous I/O
DDR registers in I/O cells
Dedicated read/write levelling functionality
Dedicated gearing logic
Source synchronous standards support
— ADC/DAC, 7:1 LVDS, XGMII
— High Speed ADC/DAC devices
• Dedicated DDR2/DDR3 and LPDDR2/LPDDR3
memory support with DQS logic, up to 800 Mbps
data-rate
•
•
•
•
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1-1
DS1044
Introduction_01.2
Introduction
ECP5 Family Data Sheet
Table 1-1. ECP5 Family Selection Guide
Device
LUTs (K)
sysMEM Blocks (18 Kbits)
Embedded Memory (Kbits)
Distributed RAM Bits (Kbits)
18 X 18 Multipliers
SERDES (Dual/Channels)
PLLs/DLLs
285 csfBGA (10 x 10 mm
2
, 0.5 mm)
381 caBGA (17 x 17 mm
2
)
554 caBGA (23 x 23 mm )
756 caBGA (27 x 27 mm
2
)
2
LFE5UM-25
24
56
1,008
194
28
1/2
2/2
2/118
2/197
LFE5UM-45
44
108
1944
351
72
2/4
4/4
2/118
4/203
4/245
LFE5UM-85
84
208
3744
669
156
2/4
4/4
2/118
4/205
4/259
4/365
LFE5U-25
24
56
1,008
194
28
0
2/2
0/118
0/197
LFE5U-45
44
108
1944
351
72
0
4/4
0/118
0/203
0/245
LFE5U-85
84
208
3744
669
156
0
4/4
0/118
0/205
0/259
0/365
Packages and SERDES Channels / I/O Combinations
Introduction
The ECP5 family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP
architecture, high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric.
This combination is achieved through advances in device architecture and the use of 40nm technology making the
devices suitable for high-volume, high-speed, low-cost applications.
The ECP5 device family covers look-up-table (LUT) capacity to 84K logic elements and supports up to 365 user I/Os.
The ECP5 device family also offers up to 156 18 x 18 multipliers and a wide range of parallel I/O standards.
The ECP5 FPGA fabric is optimized high performance with low power and low cost in mind. The ECP5 devices uti-
lize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distrib-
uted and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source
synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and
dual-boot capabilities.
The pre-engineered source synchronous logic implemented in the ECP5 device family supports a broad range of
interface standards, including DDR2/3, LPDDR2/3, XGMII and 7:1 LVDS.
The ECP5 device family also features high speed SERDES with dedicated PCS functions. High jitter tolerance and
low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular data proto-
cols including PCI Express, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit De-emphasis with pre- and
post- cursors, and Receive Equalization settings make the SERDES suitable for transmission and reception over
various forms of media.
The ECP5 devices also provide flexible, reliable and secure configuration options, such as dual-boot capability, bit-
stream encryption, and TransFR field upgrade features.
The Lattice Diamond™ design software allows large complex designs to be efficiently implemented using the
ECP5 FPGA family. Synthesis library support for ECP5 devices is available for popular logic synthesis tools. The
Diamond tools use the synthesis tool output along with the constraints from its floor planning tools to place and
route the design in the ECP5 device. The tools extract the timing from the routing and back-annotate it into the
design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) modules for the ECP5 family. By using these con-
figurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their
design, increasing their productivity.
1-2
ECP5 Family Data Sheet
Architecture
August 2015
Preliminary Data Sheet DS1044
Architecture Overview
Each ECP5 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed
between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sysDSP™ Dig-
ital Signal Processing slices, as shown in Figure 2-1. The LFE5-85 devices have three rows of DSP slices, the
LFE5-45 devices have two rows and LFE5-25 devices have one. In addition, the LFE5UM devices contain
SERDES Duals on the bottom of the device.
The Programmable Functional Unit (PFU) contains the building blocks for logic, arithmetic, RAM and ROM func-
tions. The PFU block is optimized for flexibility, allowing complex designs to be implemented quickly and efficiently.
Logic Blocks are arranged in a two-dimensional array.
The ECP5 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large, dedicated 18 Kbit
fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths as RAM or ROM. In
addition, ECP5 devices contain up to three rows of DSP slices. Each DSP slice has multipliers and adder/accumu-
lators, which are the building blocks for complex signal processing capabilities.
The ECP5 devices feature up to 4 embedded 3.2 Gbps SERDES (Serializer / Deserializer) channels. Each
SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic. Each
group of two SERDES channels, along with its Physical Coding Sub-layer (PCS) block, creates a dual DCU (Dual
Channel Unit). The functionality of the SERDES/PCS duals can be controlled by SRAM cell settings during device
configuration or by registers that are addressable during device operation. The registers in every dual can be pro-
grammed via the SERDES Client Interface (SCI). These DCUs (up to two) are located at the bottom of the devices.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the
ECP5 devices are arranged in seven banks (eight banks for LFE5-85 devices in caBGA756 and caBGA554 pack-
ages), allowing the implementation of a wide variety of I/O standards. One of these banks (Bank 8) is shared with
the programming interfaces. 50% of the PIO pairs on the left and right edges of the device can be configured as
LVDS transmit pairs, and all pairs on left and right can be configured as LVDS receive pairs. The PIC logic in the left
and right banks also includes pre-engineered support to aid in the implementation of high speed source synchro-
nous standards such as XGMII, 7:1 LVDS, along with memory interfaces including DDR3 and LPDDR3.
The ECP5 registers in PFU and sysI/O can be configured to be SET or RESET. After power up and the device is
configured, it enters into user mode with these registers SET/RESET according to the configuration setting, allow-
ing the device entering to a known state for predictable system function.
Other blocks provided include PLLs, DLLs and configuration functions. The ECP5 architecture provides up to four
Delay Locked Loops (DLLs) and up to four Phase Locked Loops (PLLs). The PLL and DLL blocks are located at the
corners of each device.
The configuration block that supports features such as configuration bit-stream decryption, transparent updates
and dual-boot support is located at the bottom of each device, to the left of the SERDES blocks. Every device in the
ECP5 family supports a sysCONFIG™ ports located in that same corner, powered by Vccio8, allowing for serial or
parallel device configuration.
In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error
detect capability. The ECP5 devices use 1.1 V as their core voltage.
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
DS1044
Architecture_01.2
Architecture
ECP5 Family Data Sheet
Figure 2-1. Simplified Block Diagram, LFE5UM-85 Device (Top Level)
DLL
DLL
PLL
sysCLOCK PLLs:
Frequency
synthesis and
balanced
PCLK
tress
sysIO Bank 0
sysIO Bank 1
PLL
sysCLOCK DLLs:
Accurate phase
alignments
Enhanced DSP
Slices:
Multiply,
Accumulate,
and ALU
Pre-engineered
Source
Synchronous
Support:
DDR3, LPDDR3 –
800
Mbps
Generic – Up to
800
Mbps
Flexible sysIO
(Bank 4 is on
LFE5-85 only):
LVCMOS, SSTL,
HSUL, LVDS
sysIO Bank 7
sysIO Bank 6
sysMEM Block
RAM:
18 kbit EBRs
sysIO Bank 3
sysIO Bank 2
Programmable
Functional Units:
Up to
84K
LUTs
SERDES DCU0
SERDES DCU1
Flexible Routing:
Optimized for speed,
power and routability
PLL
DLL
sysConfig, JTAG & On-Chip Oscillator
sysIO Bank
8
DCU0
DCU0
Channel 0
Channel 1
DCU1
DCU1
Channel 0 Channel 1
PLL
sysIO Bank 4
DLL
Dual Function
sysIO Pins:
Shared I/Os for
sysConfig
3.2 Gbps SERDES
Note:
There is no Bank 4 in LFE5-25 and LFE5-45.
There are no PLL and DLL on the top corners in LFE5-25.
2-2
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