LH7A400
Preliminary data sheet
FEATURES
• 32-bit ARM9TDMI™ RISC Core
– 16 kB Cache: 8 kB Instruction and 8 kB Data
– MMU (Windows CE™ Enabled)
– Up to 250 MHz; see Table 1 for options
• 80 kB On-Chip Static RAM
• Programmable Interrupt Controller
• External Bus Interface
– Up to 125 MHz; see Table 1 for options
– Asynchronous SRAM/ROM/Flash
– Synchronous DRAM/Flash
– PCMCIA
– CompactFlash
• Clock and Power Management
– 32.768 kHz and 14.7456 MHz Oscillators
– Programmable PLL
• Programmable LCD Controller
– Up to 1,024 × 768 Resolution
– Supports STN, Color STN, AD-TFT, HR-TFT, TFT
– Up to 64 k-Colors and 15 Gray Shades
• DMA (10 Channels)
– AC97
– MMC
– USB
• USB Device Interface (USB 2.0, Full Speed)
• Synchronous Serial Port (SSP)
– Motorola SPI™
– Texas Instruments SSI
– National MICROWIRE™
32-Bit System-on-Chip
• Three Programmable Timers
• Three UARTs
– Classic IrDA (115 kbit/s)
• Smart Card Interface (ISO7816)
• Two DC-to-DC Converters
• MultiMediaCard™ Interface
• AC97 Codec Interface
• Smart Battery Monitor Interface
• Real Time Clock (RTC)
• Up to 60 General Purpose I/Os
• Watchdog Timer
• JTAG Debug Interface and Boundary Scan
• Operating Voltage
– 1.8 V Core
– 3.3 V Input/Output
• 5 V Tolerant Digital Inputs (except oscillator pins)
– Oscillator pins P15, P16, R13, and T13 are
1.8 V ± 10 %.
• Operating Temperature:
−40°C
to +85°C
• 256-ball BGA or 256-ball LFBGA Package
DESCRIPTION
The LH7A400, powered by an ARM922T, is a com-
plete System-on-Chip with a high level of integration to
satisfy a wide range of requirements and expectations.
This high degree of integration lowers overall
system costs, reduces development cycle time and
accelerates product introduction.
Table 1. LH7A400 versions
PART NUMBER
LH7A400N0F076B5
LH7A400N0F000B3A
LH7A400N0F000B5
LH7A400N0G000B5
CORE
CLOCK
250 MHz/
245 MHz
200 MHz/
195 MHz
200 MHz/
195 MHz
200 MHz/
195 MHz
BUS
CLOCK
125 MHz
100 MHz
100 MHz
100 MHz
LOW POWER CURRENT BY MODE (TYP.)
Run = 250 mA; Halt = 50 mA; Standby = 129
µA
Run = 125 mA; Halt: 25 mA; Standby = 42
µA
Run = 125 mA; Halt: 25 mA; Standby = 42
µA
Run = 125 mA; Halt: 25 mA; Standby = 42
µA
TEMP. RANGE
0°C to +70°C/
−
40°C to +85°C
0°C to +70°C/
−
40°C to +85°C
0°C to +70°C/
−
40°C to +85°C
0°C to +70°C/
−
40°C to +85°C
Preliminary data sheet
1
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
Table 2. Ordering information
Package
Type number
Name
LH7A400N0G000B5
LH7A400N0F000B3A
LH7A400N0F000B5
LH7A400N0F076B5
BGA256
LFBGA256
LFBGA256
LFBGA256
Description
plastic ball grid array package; 256 balls
plastic low profile fine-pitch ball grid array
package; 256 balls
plastic low profile fine-pitch ball grid array
package; 256 balls
plastic low profile fine-pitch ball grid array
package; 256 balls
SOT1018-1
SOT1020-1
SOT1020-1
SOT1020-1
Version
2
Rev. 01
—
16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
LH7A400
14.7456 MHz
32.768 kHz
OSCILLATOR,
PLL1 and PLL2, POWER
MANAGEMENT, and
RESET CONTROL
REAL TIME
CLOCK
WATCHDOG
TIMER
ARM922T
INTERRUPT
CONTROLLER
STATIC
(ASYNCHRONOUS)
MEMORY
CONTROLLER
(SMC)
EXTERNAL
BUS
INTERFACE
PCMCIA/CF
CONTROLLER
SYNCHRONOUS
DYNAMIC RAM
CONTROLLER
(SDMC)
LCD AHB
BUS
80KB
SRAM
TIMER (3)
GENERAL
PURPOSE I/O
(60)
SYNCHRONOUS
SERIAL PORT
BATTERY
MONITOR
INTERFACE
UART (3)
IrDA
INTERFACE
USB DEVICE
INTERFACE
MULTIMEDIACARD
INTERFACE
ADVANCED AUDIO
CODEC (AC97)
ADVANCED
PERIPHERAL
BUS BRIDGE
COLOR LCD
CONTROLLER
DMA
CONTROLLER
ADVANCED LCD
INTERFACE
AUDIO CODEC
INTERFACE
SMART CARD
INTERFACE
(ISO7816)
DC to DC
INTERFACE
(2)
ADVANCED
HIGH-PERFORMANCE
BUS (AHB)
ADVANCED
PERPHERAL
BUS (APB)
LH7A400-1
Figure 1. LH7A400 block diagram
Preliminary data sheet
Rev. 01
—
16 July 2007
3
LH7A400
NXP Semiconductors
32-Bit System-on-Chip
ball A1
index area
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
LH7A400
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
002aad223
Transparent top view
Figure 2. Pin configuration (BGA256)
ball A1
index area
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
LH7A400
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
002aad224
Transparent top view
Figure 3. Pin configuration (LFBGA256)
4
Rev. 01
—
16 July 2007
Preliminary data sheet
32-Bit System-on-Chip
NXP Semiconductors
LH7A400
Table 3. Functional Pin List
BGA
PIN
G7
F1
K7
M1
M5
T6
R14
M14
J11
J12
F13
B14
E10
B8
H7
G3
K4
N5
P6
T14
R16
N16
K13
H9
C15
A11
E8
A5
F7
E1
J4
P3
T8
K9
L13
E15
D12
A7
H5
M3
L9
T10
N15
H12
B15
C9
G6
LFBGA
PIN
C10
F9
F11
F14
G8
H13
J9
K15
L7
N6
N8
N12
N13
P11
B8
C6
D5
D13
E8
F7
G13
H9
J14
K7
L8
L10
L12
M11
M14
C4
D7
D10
F4
F10
J4
J8
K8
L6
G7
H4
H8
L4
L9
N3
N7
N10
R5
VSSC
Core Ground
VDDC
Core Power
VSS
I/O Ring Ground
VDD
I/O Ring Power
SIGNAL
DESCRIPTION
RESET
STATE
STANDBY
STATE
OUTPUT I/O NOTES
DRIVE
Preliminary data sheet
Rev. 01
—
16 July 2007
5
