LPC2114/2124
Single-chip 16/32-bit microcontrollers; 128/256 kB ISP/IAP
flash with 10-bit ADC
Rev. 7 — 10 June 2011
Product data sheet
1. General description
The LPC2114/2124 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation
and embedded trace support, together with 128/256 kB of embedded high-speed flash
memory. A 128-bit wide memory interface and a unique accelerator architecture enable
32-bit code execution at maximum clock rate. For critical code size applications, the
alternative 16-bit Thumb mode reduces code by more than 30 % with minimal
performance penalty.
With their compact 64-pin package, low power consumption, various 32-bit timers,
4-channel 10-bit ADC, PWM channels and 46 fast GPIO lines with up to nine external
interrupt pins these microcontrollers are particularly suitable for industrial control, medical
systems, access control and point-of-sale. With a wide range of serial communications
interfaces, they are also very well suited for communication gateways, protocol converters
and embedded soft modems as well as many other general-purpose applications.
Remark:
Throughout the data sheet, the term LPC2114/2124 will apply to devices with
and without the /00 or /01 suffixes. The /00 or the /01 suffix will be used to differentiate
from other devices only when necessary.
2. Features and benefits
2.1 Key features brought by LPC2114/2124/01 devices
Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original device.
They also allow for a port pin to be read at any time regardless of its function.
Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are
5 V tolerant when configured for digital I/O function(s).
UART0/1 include fractional baud rate generator, auto-bauding capabilities and
handshake flow-control fully implemented in hardware.
Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.
SPI programmable data length and master mode enhancement.
Diversified Code Read Protection (CRP) enables different security levels to be
implemented. This feature is available in LPC2114/2124/00 devices as well.
General purpose timers can operate as external event counters.
2.2 Key features common for all devices
16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
16 kB on-chip static RAM.
NXP Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
128/256 kB on-chip flash program memory. 128-bit wide interface/accelerator enables
high speed 60 MHz operation.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or
full chip erase takes 400 ms.
EmbeddedICE-RT interface enables breakpoints and watch points. Interrupt service
routines can continue to execute whilst the foreground task is debugged with the
on-chip RealMonitor software.
Embedded Trace Macrocell (ETM) enables non-intrusive high speed real-time tracing
of instruction execution.
Four-channel 10-bit ADC with conversion time as low as 2.44
s.
Two 32-bit timers (with four capture and four compare channels), PWM unit (six
outputs), Real-Time Clock (RTC) and watchdog.
Multiple serial interfaces including two UARTs (16C550), Fast I
2
C-bus (400 kbit/s) and
two SPIs.
60 MHz maximum CPU clock available from programmable on-chip Phase-Locked
Loop with settling time of 100
s.
Vectored Interrupt Controller with configurable priorities and vector addresses.
Up to forty-six 5 V tolerant general purpose I/O pins. Up to nine edge or level sensitive
external interrupt pins available.
On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.
Two low power modes, Idle and Power-down.
Processor wake-up from Power-down mode via external interrupt.
Individual enable/disable of peripheral functions for power optimization.
Dual power supply:
CPU operating voltage range of 1.65 V to 1.95 V (1.8 V
0.15 V).
I/O power supply range of 3.0 V to 3.6 V (3.3 V
10 %) with 5 V tolerant I/O pads.
16/32-bit ARM7TDMI-S processor.
3. Ordering information
Table 1.
Ordering information
Package
Name
LPC2114FBD64/01
LPC2124FBD64/01
LQFP64
LQFP64
Description
plastic low profile quad flat package; 64 leads;
body 10
10
1.4 mm
plastic low profile quad flat package; 64 leads;
body 10
10
1.4 mm
Version
SOT314-2
SOT314-2
Type number
LPC2114_2124
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 10 June 2011
2 of 42
NXP Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
3.1 Ordering options
Table 2.
Ordering options
Flash
memory
RAM
Fast GPIO/SSP/
Enhanced
UART, ADC,
Timer
yes
yes
Temperature range
Type number
LPC2114FBD64/01
LPC2124FBD64/01
128 kB
256 kB
16 kB
16 kB
40 C
to +85
C
40 C
to +85
C
LPC2114_2124
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 10 June 2011
3 of 42
NXP Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
4. Block diagram
TMS
(2)
TDI
(2)
RTCK
(2)
TRST
(2)
TCK
(2)
TDO
(2)
XTAL2
XTAL1
RESET
EMULATION
TRACE MODULE
LPC2114
LPC2124
P0[30:27],
P0[25:0]
P1[31:16]
HIGH-SPEED
GPIO
(3)
46 PINS TOTAL
TEST/DEBUG
INTERFACE
PLL
system
clock
SYSTEM
FUNCTIONS
VECTORED
INTERRUPT
CONTROLLER
ARM7TDMI-S
AHB BRIDGE
ARM7 LOCAL BUS
AMBA Advanced High-performance
Bus (AHB)
INTERNAL
SRAM
CONTROLLER
MEMORY
ACCELERATOR
AHB
DECODER
AHB TO APB
BRIDGE
APB
DIVIDER
16 kB
SRAM
128/256 kB
FLASH
EINT[3:0]
(1)
EXTERNAL
INTERRUPTS
I
2
C-BUS SERIAL
INTERFACE
SCL
(1)
SDA
(1)
SCK0
(1)
4
×
CAP0
(1)
4
×
CAP1
(1)
4
×
MAT0
(1)
4
×
MAT1
(1)
AIN[3:0]
(1)
CAPTURE/
COMPARE
TIMER 0/TIMER 1
SPI0
SERIAL INTERFACE
MOSI0
(1)
MISO0
(1)
SSEL0
(1)
SCK1
(1)
A/D CONVERTER
SPI1/SSP
(3)
SERIAL INTERFACE
MOSI1
(1)
MISO1
(1)
SSEL1
(1)
P0[30:27],
P0[25:0]
P1[31:16]
GENERAL
PURPOSE I/O
UART0/UART1
TXD[1:0]
(1)
RXD[1:0]
(1)
DSR1
(1)
, CTS1
(1)
,
RTS1
(1)
, DTR1
(1)
,
DCD1
(1)
, RI1
(1)
PWM0
WATCHDOG
TIMER
PWM[6:1]
(1)
REAL-TIME CLOCK
SYSTEM
CONTROL
002aad175
(1) Shared with GPIO.
(2) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
(3) SSP interface and high-speed GPIO are available on LPC2114/01 and LPC2124/01 only.
Fig 1.
Block diagram
LPC2114_2124
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 10 June 2011
4 of 42
NXP Semiconductors
LPC2114/2124
Single-chip 16/32-bit microcontrollers
5. Pinning information
5.1 Pinning
54 P0[19]/MAT1[2]/MOSI1/CAP1[2]
53 P0[18]/CAP1[3]/MISO1/MAT1[3]
55 P0[20]/MAT1[3]/SSEL1/EINT3
64 P1[27]/TDO
52 P1[30]/TMS
56 P1[29]/TCK
60 P1[28]/TDI
63 V
DDA(1V8)
58 V
SSA(PLL)
51 V
DD(3V3)
P0[21]/PWM5/CAP1[3]
P0[22]/CAP0[0]/MAT0[0]
P0[23]
P1[19]/TRACEPKT3
P0[24]
V
SS
V
DDA(3V3)
P1[18]/TRACEPKT2
P0[25]
1
2
3
4
5
6
7
8
9
50 V
SS
49 V
DD(1V8)
48 P1[20]/TRACESYNC
47 P0[17]/CAP1[2]/SCK1/MAT1[2]
46 P0[16]/EINT0/MAT0[2]/CAP0[2]
45 P0[15]/RI1/EINT2
44 P1[21]/PIPESTAT0
43 V
DD(3V3)
42 V
SS
41 P0[14]/DCD1/EINT1
40 P1[22]/PIPESTAT1
39 P0[13]/DTR1/MAT1[1]
38 P0[12]/DSR1/MAT1[0]
37 P0[11]/CTS1/CAP1[1]
36 P1[23]/PIPESTAT2
35 P0[10]/RTS1/CAP1[0]
34 P0[9]/RXD1/PWM6/EINT3
33 P0[8]/TXD1/PWM4
P0[7]/SSEL0/PWM2/EINT2 31
P1[24]/TRACECLK 32
002aad176
LPC2114
LPC2124
(1)
n.c. 10
P0[27]/AIN0/CAP0[1]/MAT0[1] 11
P1[17]/TRACEPKT1 12
P0[28]/AIN1/CAP0[2]/MAT0[2] 13
P0[29]/AIN2/CAP0[3]/MAT0[3] 14
P0[30]/AIN3/EINT3/CAP0[0] 15
P1[16]/TRACEPKT0 16
V
DD(1V8)
17
V
SS
18
P0[0]/TXD0/PWM1 19
P1[31]/TRST 20
P0[1]/RXD0/PWM3/EINT0 21
P0[2]/SCL/CAP0[0] 22
V
DD(3V3)
23
P1[26]/RTCK 24
57 RESET
62 XTAL1
61 XTAL2
59 V
SSA
V
SS
25
P0[3]/SDA/MAT0[0]/EINT1 26
P0[4]/SCK0/CAP0[1] 27
P1[25]/EXTIN0 28
P0[5]/MISO0/MAT0[1] 29
(1) Pin configuration is identical for devices with and without the /00 and /01 suffixes.
Fig 2.
Pin configuration
LPC2114_2124
All information provided in this document is subject to legal disclaimers.
P0[6]/MOSI0/CAP0[2] 30
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 10 June 2011
5 of 42
