LPC2420/2460
Flashless 16-bit/32-bit microcontroller; Ethernet, CAN,
ISP/IAP, USB 2.0 device/host/OTG, external memory interface
Rev. 04 — 15 October 2009
Preliminary data sheet
1. General description
NXP Semiconductors designed the LPC2420/2460 microcontroller around a 16-bit/32-bit
ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and
embedded trace. The LPC2420/2460 is flashless. The LPC2420/2460 can execute both
32-bit ARM and 16-bit Thumb instructions. Support for the two instruction sets means
engineers can choose to optimize their application for either performance or code size at
the sub-routine level. When the core executes instructions in Thumb state it can reduce
code size by more than 30 % with only a small loss in performance while executing
instructions in ARM state maximizes core performance.
The LPC2420/2460 microcontroller is ideal for multi-purpose communication applications.
It incorporates a 10/100 Ethernet Media Access Controller (MAC) (LPC2460 only), a USB
full-speed device/host/OTG controller with 4 kB of endpoint RAM, four UARTs, two
Controller Area Network (CAN) channels (LPC2460 only), an SPI interface, two
Synchronous Serial Ports (SSP), three I
2
C interfaces, and an I
2
S interface. Supporting
this collection of serial communications interfaces are the following feature components;
an on-chip 4 MHz internal precision oscillator, 82/98 kB of total RAM consisting of 64 kB
of local SRAM, 16 kB SRAM for Ethernet (LPC2460 only), 16 kB SRAM for general
purpose DMA, 2 kB of battery powered SRAM, and an External Memory Controller
(EMC). These features make this device optimally suited for communication gateways and
protocol converters. Complementing the many serial communication controllers, versatile
clocking capabilities, and memory features are various 32-bit timers, an improved 10-bit
ADC, 10-bit DAC, two PWM units, four external interrupt pins, and up to 160 fast GPIO
lines. The LPC2420/2460 connects 64 of the GPIO pins to the hardware based Vector
Interrupt Controller (VIC) that means these external inputs can generate edge-triggered
interrupts. All of these features make the LPC2420/2460 particularly suitable for industrial
control and medical systems.
2. Features
I
ARM7TDMI-S processor, running at up to 72 MHz.
I
82/98 kB on-chip SRAM includes:
N
64 kB of SRAM on the ARM local bus for high performance CPU access.
N
16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
(LPC2460 only)
N
16 kB SRAM for general purpose DMA use also accessible by the USB.
N
2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.
I
Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet
DMA, and USB DMA with no contention (LPC2460 only).
NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
I
EMC provides support for asynchronous static memory devices such as RAM, ROM
and flash, as well as dynamic memories such as single data rate SDRAM.
I
Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
I
General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP,
I
2
S, and SD/MMC interface as well as for memory-to-memory transfers.
I
Serial Interfaces:
N
Ethernet MAC with MII/RMII interface and associated DMA controller (LPC2460
only). These functions reside on an independent AHB.
N
USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and
associated DMA controller.
N
Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO.
N
CAN controller with two channels (LPC2460 only).
N
SPI controller.
N
Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA
controller.
N
Three I
2
C-bus interfaces (one with open-drain and two with standard port pins).
N
I
2
S (Inter-IC Sound) interface for digital audio input or output. It can be used with
the GPDMA.
I
Other peripherals:
N
SD/MMC memory card interface.
N
160 General purpose I/O pins with configurable pull-up/down resistors.
N
10-bit ADC with input multiplexing among 8 pins.
N
10-bit DAC.
N
Four general purpose timers/counters with 8 capture inputs and 10 compare
outputs. Each timer block has an external count input.
N
Two PWM/timer blocks with support for three-phase motor control. Each PWM has
an external count inputs.
N
RTC with separate power domain. Clock source can be the RTC oscillator or the
APB clock.
N
2 kB SRAM powered from the RTC power pin, allowing data to be stored when the
rest of the chip is powered off.
N
WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock.
I
Standard ARM test/debug interface for compatibility with existing tools.
I
Emulation trace module supports real-time trace.
I
Single 3.3 V power supply (3.0 V to 3.6 V).
I
Four reduced power modes: idle, sleep, power-down, and deep power-down.
I
Four external interrupt inputs configurable as edge/level sensitive. All pins on port 0
and port 2 can be used as edge sensitive interrupt sources.
I
Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, port 0/2
pin interrupt, Ethernet wake-up interrupt (LPC2460 only), CAN bus activity (LPC2460
only)).
I
Two independent power domains allow fine tuning of power consumption based on
needed features.
LPC2420_60_4
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 04 — 15 October 2009
2 of 78
NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
I
Each peripheral has its own clock divider for further power saving. These dividers help
reduce active power by 20 % to 30 %.
I
Brownout detect with separate thresholds for interrupt and forced reset.
I
On-chip power-on reset.
I
On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
I
4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as
the system clock. When used as the CPU clock, does not allow CAN and USB to run.
I
On-chip PLL allows CPU operation up to the maximum CPU rate without the need for
a high frequency crystal. May be run from the main oscillator, the internal RC
oscillator, or the RTC oscillator.
I
Boundary scan for simplified board testing.
I
Versatile pin function selections allow more possibilities for using on-chip peripheral
functions.
3. Applications
I
I
I
I
Industrial control
Medical systems
Protocol converter
Communications
4. Ordering information
Table 1.
Ordering information
Package
Name
LPC2420FBD208 LQFP208
LPC2460FBD208 LQFP208
Description
plastic low profile quad flat package; 208 leads; body 28
×
28
×
1.4 mm
plastic low profile quad flat package; 208 leads; body 28
×
28
×
1.4 mm
Version
SOT459-1
SOT459-1
Type number
LPC2420FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15
×
15
×
0.7 mm SOT950-1
LPC2460FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15
×
15
×
0.7 mm SOT950-1
LPC2420_60_4
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 04 — 15 October 2009
3 of 78
NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
4.1 Ordering options
Table 2.
Ordering options
Flash
(kB)
Local bus
SRAM (kB)
Ethernet buffer
External
bus
Ethernet
USB
OTG/
OHCI/
device
+ 4 kB
FIFO
SD/ GP
MMC DMA
CAN channels
ADC channels
DAC channels
1
1
1
1
−40 °C
to
+85
°C
−40 °C
to
+85
°C
−40 °C
to
+85
°C
−40 °C
to
+85
°C
Temp
range
Type number
GP/USB
LPC2420FBD208
LPC2420FET208
LPC2460FBD208
LPC2460FET208
N/A
N/A
N/A
N/A
64 -
16 2
82 Full 32-bit
98 Full 32-bit
98 Full 32-bit
98 Full 32-bit
Total
RTC
-
MII/RMII
MII/RMII
MII/RMII
yes
yes
yes
yes
-
2
2
2
yes
yes
yes
yes
yes
yes
yes
yes
8
8
8
8
64 16 16 2
64 16 16 2
64 16 16 2
LPC2420_60_4
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 04 — 15 October 2009
4 of 78
NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
5. Block diagram
XTAL1
V
DD(3V3)
XTAL2
V
DDA
TMS TDI
trace signals
TRST
TCK TDO
EXTIN0 DBGEN
RESET
VREF
V
SSA
, V
SSCORE
, V
SSIO
V
DD(DCDC)(3V3)
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
P0, P1, P2,
P3, P4
LPC2420/2460
64 kB
SRAM
PLL
system
clock
SYSTEM
FUNCTIONS
INTERNAL RC
OSCILLATOR
HIGH-SPEED
GPI/O
160 PINS
TOTAL
INTERNAL
SRAM
CONTROLLER
ARM7TDMI-S
VIC
16 kB
SRAM
EXTERNAL
MEMORY
CONTROLLER
AHB1
D[31:0]
A[23:0]
control lines
AHB2
AHB
BRIDGE
AHB
BRIDGE
USB DEVICE/
HOST/OTG WITH
4 kB RAM AND DMA
GP DMA
CONTROLLER
I2SRX_CLK
I2STX_CLK
I2SRX_WS
I2STX_WS
I2SRX_SDA
I2STX_SDA
SCK, SCK0
MOSI, MOSI0
MISO, MISO0
SSEL, SSEL0
SCK1
MOSI1
MISO1
SSEL1
MCICLK, MCIPWR
MCICMD,
MCIDAT[3:0]
TXD0, TXD2, TXD3
RXD0, RXD2, RXD3
TXD1
RXD1
DTR1, RTS1
DSR1, CTS1, DCD1,
RI1
CAN1
(1)
, CAN2
(1)
RD1, RD2
TD1, TD2
SCL0, SCL1, SCL2
SDA0, SDA1, SDA2
V
BUS
port1
port2
MII/RMII
ETHERNET
MAC WITH
DMA
(1)
16 kB
SRAM
(1)
MASTER AHB TO SLAVE
PORT AHB BRIDGE PORT
AHB TO
APB BRIDGE
EINT3 to EINT0
P0, P2
2
×
CAP0/CAP1/
CAP2/CAP3
4
×
MAT2/MAT3,
2
×
MAT0,
3
×
MAT1
6
×
PWM0/PWM1
1
×
PCAP0,
2
×
PCAP1
P0, P1
EXTERNAL INTERRUPTS
CAPTURE/COMPARE
TIMER0/TIMER1/
TIMER2/TIMER3
I
2
S INTERFACE
PWM0, PWM1
SPI, SSP0 INTERFACE
LEGACY GPI/O
64 PINS TOTAL
SSP1 INTERFACE
8
×
AD0
A/D CONVERTER
SD/MMC CARD
INTERFACE
AOUT
VBAT
power domain 2
RTCX1
RTCX2
ALARM
D/A CONVERTER
UART0, UART2, UART3
2 kB BATTERY RAM
RTC
OSCILLATOR
REAL-
TIME
CLOCK
UART1
WATCHDOG TIMER
SYSTEM CONTROL
I
2
C0, I
2
C1, I
2
C2
002aad313
(1) LPC2460 only.
Fig 1. LPC2420/2460 block diagram
LPC2420_60_4
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 04 — 15 October 2009
5 of 78
