interface and power supply controller featuring 2-event
classification signaling, flexible auxiliary power op-
tions, and a power supply controller suitable for syn-
chronously rectified forward supplies. These features
make the LTC4269-2 ideally suited for an IEEE802.3at
PD application.
The PD controller features a 100V MOSFET that isolates
the power supply during detection and classification, and
provides 100mA inrush current limit. Also included are
power good outputs, an undervoltage/overvoltage lock-
out and thermal protection. The current mode forward
controller allows for synchronous rectification, resulting
in an extremely high efficiency, green product. Soft-start
for controlled output voltage start-up and fault recovery is
included. Programmable frequency over 100kHz to 500kHz
allows flexibility in efficiency vs size and low EMI.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Hot Swap, ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
n
n
n
n
n
n
n
25.5W IEEE 802.3at Compliant (Type-2) PD
PoE
+
2-Event Classification
IEEE 802.3at
High Power Available
Indicator
Integrated State-of-the-Art Synchronous Forward
Controller
– Isolated Power Supply Efficiency >94%
Flexible Auxiliary Power Interface
Superior EMI Performance
Robust 100V 0.7Ω (Typ) Integrated Hot Swap™
MOSFET
Integrated Signature Resistor, Programmable Class
Current, UVLO, OVLO and Thermal Protection
Short-Circuit Protection with Auto-Restart
Programmable Switching Frequency from
100kHz to 500kHz
Thermally Enhanced 7mm
×
4mm DFN Package
applicaTions
n
n
n
IP Phones with Large Color Screens
Dual Radio 802.11n Access Points
PTZ Security Cameras
Typical applicaTion
PoE-Based Self-Driven Synchronous Forward Power Supply
1mH
•
10µH
6.8µH
•
2.2µF
33k
V
CC
0.1µF
10µF
133
SD_V
SEC
PWRGD V
IN
V
PORTP
S
OUT
10k
4.7nF
+
•
5.1
+
5V
5A
220µF
10µF
237k
10.0k
+
54V FROM
DATA PAIR
~ +
~ –
~ +
~ –
0.1µF
30.9
OUT
54V FROM
SPARE PAIR
OC
I
SENSE
V
CC
1.5k
33k
22k
1.2k
22.1k
0.1µF
0.22µF
TLV431
50m
4.7nF
2k
10nF
11.3k
R
CLASS
SHDN
V
PORTN
LTC4269-2
COMP
FB
V
REF
T2P
V
NEG
PGND GND BLANK DELAY R
OSC
SS_MAXDC
82k
332k
158k
158k
3.65k
42692 TA01
TO
MICRO-
CONTROLLER
42692fb
LTC4269-2
absoluTe MaxiMuM raTings
(Notes 1, 2)
pin conFiguraTion
TOP VIEW
SHDN 1
T2P
2
R
CLASS
3
NC 4
V
PORTN
5
V
PORTN
6
NC 7
NC 8
COMP 9
FB 10
R
OSC
11
SYNC 12
SS_MAXDC 13
V
REF
14
SD_V
SEC
15
GND 16
32 V
PORTP
31 NC
30 NC
29
PWRGD
28 PWRGD
27 V
NEG
26 V
NEG
25 NC
24 SOUT
23 V
IN
22 OUT
21 PGND
20 DELAY
19 OC
18 I
SENSE
17 BLANK
Pins with Respect to V
PORTN
V
PORTP
Voltage ........................................ –0.3V to 100V
V
NEG
Voltage ......................................... –0.3V to V
PORTP
V
NEG
Pull-Up Current ..................................................1A
SHDN ....................................................... –0.3V to 100V
R
CLASS
, Voltage ........................................... –0.3V to 7V
R
CLASS
Source Current ..........................................50mA
PWRGD Voltage (Note 3)
Low Impedance Source .... V
NEG
– 0.3V to V
NEG
+ 11V
Sink Current .........................................................5mA
PWRGD, T2P
Voltage ............................... –0.3V to 100V
PWRGD, T2P
Sink Current .....................................10mA
Pins with Respect to GND
V
IN
(Note 4)................................................ –0.3V to 25V
SYNC, SS_MAXDC, SD_V
SEC
,
I
SENSE
, OC .................................................... –0.3V to 6V
COMP, BLANK, DELAY .............................. –0.3V to 3.5V
FB ................................................................ –0.3V to 3V
R
OSC
Current ........................................................ –50µA
V
REF
Source Current ..............................................10mA
Operating Ambient Temperature Range
LTC4269C-2 ............................................. 0°C to 70°C
LTC4269I-2 ..........................................–40°C to 85°C
33
DKD PACKAGE
32-LEAD (7mm 4mm) PLASTIC DFN
T
JMAX
= 125°C,
θ
JA
= 34°C/W,
θ
JC
= 2°C/W
EXPOSED PAD (PIN 33) MUST BE SOLDERED TO
HEAT SINKING PLANE THAT IS CONNECTED TO GND
orDer inForMaTion
LEAD FREE FINISH
LTC4269CDKD-2#PBF
LTC4269IDKD-2#PBF
LEAD BASED FINISH
LTC4269CDKD-2
LTC4269IDKD-2
TAPE AND REEL
LTC4269CDKD-2#TRPBF
LTC4269IDKD-2#TRPBF
TAPE AND REEL
LTC4269CDKD-2#TR
LTC4269IDKD-2#TR
PART MARKING*
42692
42692
PART MARKING*
42692
42692
PACKAGE DESCRIPTION
32-Lead (7mm
×
4mm) Plastic DFN
32-Lead (7mm
×
4mm) Plastic DFN
PACKAGE DESCRIPTION
32-Lead (7mm
×
4mm) Plastic DFN
32-Lead (7mm
×
4mm) Plastic DFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
42692fb
LTC4269-2
elecTrical characTerisTics
PARAMETER
Interface Controller (Note 5)
Operating Input Voltage
Signature Range
Classification Range
On Voltage
Undervoltage Lockout
Overvoltage Lockout
ON/UVLO Hysteresis Window
Signature/Class Hysteresis Window
Reset Threshold
Supply Current
Supply Current at 57V
Class O Current
Signature
Signature Resistance
Invalid Signature Resistance, SHDN Invoked
Invalid Signature Resistance During Mark Event
Classification
Class Accuracy
Classification Stability Time
Normal Operation
Inrush Current
Power FET On-Resistance
Power FET Leakage Current at V
NEG
Digital Interface
SHDN Input High Level Voltage
SHDN Input Low Level Voltage
SHDN Input Resistance
PWRGD, T2P
Output Low Voltage
PWRGD, T2P
Leakage Current
PWRGDP Output Low Voltage
PWRGDP Clamp Voltage
PWRGDP Leakage Current
PWM Controller (Note 11)
Operational Input Voltage
V
IN
Quiescent Current
V
IN
Start-Up Current
V
IN
Shutdown Current
SD_V
SEC
Threshold
I
VREF
= 0µA
I
VREF
= 0µA, I
SENSE
= OC = Open
FB = 0V, SS_MAXDC = 0V (Notes 12, 13)
SD_V
SEC
= 0V (Notes 12, 13)
10V < SD < 25V
l
l
l
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C.
CONDITIONS
At V
PORTP
(Note 6)
l
l
l
l
l
l
MIN
TYP
MAX
60
9.8
21.0
37.2
UNITS
V
V
V
V
V
V
V
V
1.5
12.5
30.0
4.1
1.4
2.57
71.0
State Machine Reset for 2-Event Classification
Measured at V
PORTP
Pin
V
PORTP
= 17.5V, No R
CLASS
Resistor
1.5V ≤ V
PORTP
≤ 9.8V (Note 7)
1.5V ≤ V
PORTP
≤ 9.8V, V
SHDN
= 3V (Note 7)
(Notes 7, 8)
10mA < I
CLASS
< 40mA, 12.5V < V
PORTP
< 21V
(Notes 9, 10)
V
PORTP
Pin Step to 17.5V, R
CLASS
= 30.9Ω,
I
CLASS
within 3.5% of Ideal Value (Notes 9, 10)
V
PORTP
= 54V, V
NEG
= 3V
Tested at 600mA into V
NEG
, V
PORTP
= 54V
V
PORTP
= SHDN = V
NEG
= 57V
l
5.40
1.35
0.40
V
mA
mA
kΩ
kΩ
kΩ
%
ms
l
l
l
l
l
23.25
26.00
11
11
±3.5
1
l
l
l
l
l
60
100
0.7
180
1.0
1
mA
Ω
µA
V
3
0.45
100
0.15
1
0.4
12.0
16.5
1
V
kΩ
V
µA
V
V
µA
V
PORTP
= 9.8V, SHDN = 9.65V
Tested at 1mA, V
PORTP
= 57V, For
T2P,
Must
Complete 2-Event Classification to See Active Low
Pin Voltage Pulled 57V, V
PORTP
= V
PORTN
= 0V
Tested at 0.5mA, V
PORTP
= 52V, V
NEG
= 4V, Output
Voltage is with Respect to V
NEG
Tested at 2mA, V
NEG
= 0V, Voltage is with Respect
to V
NEG
V
PWRGD
= 11V, V
NEG
= 0V, Voltage is with Respect
to V
NEG
l
l
l
l
l
l
V
IN(OFF)
5.2
460
240
1.261
1.32
25
6.5
700
350
1.379
V
mA
µA
µA
V
42692fb
LTC4269-2
elecTrical characTerisTics
PARAMETER
SD_V
SEC(ON)
Current
SD_V
SEC(OFF)
Current
V
IN(ON)
V
IN(OFF)
V
IN(HYST)
V
REF
Output Voltage
Line Regulation
Load Regulation
Oscillator
Frequency, f
OSC
f
OSC(MIN)
f
OSC(MAX)
SYNC Input Resistance
SYNC Switching Threshold
SYNC Frequency/f
OSC
f
OSC
Line Regulation
V
ROSC
Error Amplifier
FB Reference Voltage
FB Input Bias Current
Open-Loop Voltage Gain
Unity-Gain Bandwidth
COMP Source Current
COMP Sink Current
COMP Current (Disabled)
COMP High Level V
OH
COMP Active Threshold
COMP Low Level V
OL
Current Sense
I
SENSE
Maximum Threshold
I
SENSE
Input Current (Duty Cycle = 0%)
I
SENSE
Input Current (Duty Cycle = 80%)
OC Threshold
OC Input Current
Default Blanking Time
Adjustable Blanking Time
V
BLANK
SOUT Driver
SOUT Clamp Voltage
SOUT Low Level
I
GATE
= 0µA, COMP = 2.5V, FB = 1V
I
GATE
= 25mA
10.54
12
0.5
13.5
0.75
V
V
42692fb
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C.
CONDITIONS
SD_V
SEC
= SD_V
SEC
Threshold +100mV
SD_V
SEC
= SD_V
SEC
Threshold – 100mV
l
l
l
MIN
8.3
TYP
0
10
14.25
8.75
MAX
11.7
15.75
9.25
7.0
2.575
10
10
240
120
560
2.2
1.5
0.33
UNITS
µA
µA
V
V
V
V
mV
mV
kHz
kHz
kHz
kΩ
V
%/V
V
3.75
2.425
5.5
2.5
1
1
I
VREF
= 0
I
VREF
= 0, 10V < V
IN
< 25V
0mA < I
VREF
< 2.5mA
R
OSC
= 178k, FB = 1V, SS_MAXDC = 1.84V
R
OSC
= 365k, FB = 1V
R
OSC
= 64.9k, COMP = 2.5V, SD_V
SEC
= 2.64V
FB = 1V
FB = 1V (Note 14)
R
OSC
= 178k; 10V < V
IN
< 25V, SS_MAXDC = 1.84V
R
OSC
Pin Voltage
10V < V
IN
< 25V, V
OL
+ 0.2V < COMP < V
OH
– 0.2
FB = FB Reference Voltage
V
OL
+ 0.2V < COMP < V
OH
– 0.2
(Note 15)
FB = 1V, COMP = 1.6V
COMP = 1.6V
FB = V
REF
, COMP = 1.6V
FB = 1V, I
COMP
= –250µA
FB = 1V, SOUT Duty Cycle > 0%
I
COMP
= 250µA
COMP = 2.5V, FB =1V
COMP = 2.5V, FB = 1V (Note 12)
COMP = 2.5V, FB = 1V (Note 12)
COMP = 2.5V, FB = 1V
(OC = 100mV)
COMP = 2.5V, FB = 1V, R
BLANK
= 40k (Note 16)
COMP = 2.5V, FB = 1V, R
BLANK
= 120k
l
l
165
80
440
200
100
500
18
1.5
1.25
0.05
1
l
1.201
65
–4
4
18
2.7
0.7
1.226
-75
85
3
–9
10
23
3.2
0.8
0.15
1.250
-200
V
nA
dB
MHz
mA
mA
28
µA
V
V
0.4
243
V
mV
µA
µA
197
220
–8
–35
98
107
–50
180
540
1
116
–100
mV
nA
ns
ns
V
LTC4269-2
elecTrical characTerisTics
PARAMETER
SOUT High Level
SOUT Active Pull-Off in Shutdown
SOUT to OUT (Rise) DELAY (t
DELAY
)
V
DELAY
OUT Driver
OUT Rise Time
OUT Fall Time
OUT Clamp Voltage
OUT Low Level
OUT High Level
OUT Active Pull-Off in Shutdown
OUT Max Duty Cycle
OUT Max Duty Cycle Clamp
FB = 1V, C
L
= 1nF (Notes 15, 16)
FB = 1V, C
L
= 1nF (Notes 15, 16)
I
GATE
= 0µA, COMP = 2.5V, FB = 1V
I
GATE
= 20mA
I
GATE
= 200mA
I
GATE
= –20mA, V
IN
= 12V COMP = 2.5V, FB = 1V
I
GATE
= –200mA, V
IN
= 12V COMP = 2.5V, FB = 1V
V
IN
= 5V, SD_V
SEC
= 0V, OUT = 1V
COMP = 2.5V, FB = 1V, R
DELAY
= 10k (f
OSC
= 200kHz),
V
IN
= 10V, SD_V
SEC
= 1.4V, SS_MAXDC = V
REF
COMP = 2.5V, FB = 1V, R
DELAY
= 10k (f
OSC
= 200kHz),
V
IN
= 10V
SD_V
SEC
= 1.32V, SS_MAXDC = 1.84V
SD_V
SEC
= 2.64V, SS_MAXDC = 1.84V
I
SS_MAXDC
= 150µA, OC = 1V
Measured on SS_MAXDC
FB + 1V, DC > 0%
SS_MAXDC = 1V, SD_V
SEC
= 1.4V, OC = 1V
9.9
9.75
20
83
90
11.5
50
30
13
0.45
1.25
14.5
0.75
1.8
ns
ns
V
V
V
V
V
mA
%
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C.
CONDITIONS
I
GATE
= –25mA, V
IN
= 12V COMP = 2.5V, FB = 1V
V
IN
= 5V, SD_V
SEC
= 0V, SOUT = 1V
COMP = 2.5V, FB = 1V (Note 16)
R
DELAY
= 120k
MIN
10
1
40
120
0.9
TYP
MAX
UNITS
V
mA
ns
ns
V
63.5
25
72
33
0.2
0.45
0.8
800
80.5
41
%
%
V
V
V
µA
Soft-Start
SS_MAXDC Low Level: V
OL
SS_MAXDC Soft-Start Reset Threshold
SS_MAXDC Active Threshold
SS_MAXDC Input Current
(Soft-Start Pull-Down: I
DIS
)
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
Pins with 100V absolute maximum guaranteed for T ≥ 0°C,
otherwise 90V.
Note 3:
PWRGD voltage clamps at 14V with respect to V
NEG
.
Note 4:
In applications where the V
IN
pin is supplied via an external RC
network from a system V
IN
> 25V, an external Zener with clamp voltage
V
IN ON(MAX)
< V
Z
< 25V should be connected from the V
IN
pin to GND.
Note 5:
All voltages are with respect to V
PORTN
pin unless otherwise noted.
Note 6:
Input voltage specifications are defined with respect to LTC4269-2
pins and meet IEEE 802.3af/at specifications when the input diode bridge
is included.
Note 7:
Signature resistance is measured via the
∆V/∆I
method with the
minimum
∆V
of 1V. The LTC4269-2 signature resistance accounts for the
additional series resistance in the input diode bridge.
Note 8:
An invalid signature after the 1st classification event is mandated
by IEEE 802.3at standard. See the Applications Information section.
Note 9:
Class accuracy is respect to the ideal current defined as
1.237/R
CLASS
and does not include variations in R
CLASS
resistance.
Note 10:
This parameter is assured by design and wafer level testing.
Note 11:
Voltages are with respect to GND unless otherwise specified.
Tested with COMP open, V
FB
= 1.4V, R
ROSC
= 178k, V
SYNC
= 0V, V
SS(MAXDC)
set to V
REF
(but electrically isolated), C
VREF
= 0.1µF V
SD_VSEC
= 2V, R
BLANK
,
= 121k, R
DELAY
= 121k, V
ISENSE
= 0V, V
OC
= 0V, C
OUT
= 1nF V
IN
= 15V,
,
SOUT open, unless otherwise specified.
Note 12:
Guaranteed by correlation to static test.
Note 13:
V
IN
start-up current is measured at V
IN
= V
IN(ON)
– 0.25V and
scaled by
×
1.18 (to correlate to worst-case V
IN
start-up current at V
IN(ON)
.
Note 14:
Maximum recommended SYNC frequency = 500kHz.
Note 15:
Guaranteed but not tested.
Note 16:
Timing for R = 40k derived from measurement with R = 240k.
