M383L3313BT1
184pin Registered DDR SDRAM MODULE
256MB DDR SDRAM MODULE
(32Mx72(16Mx72*2 bank) based on 16Mx8 DDR SDRAM)
Registered 184pin DIMM
72-bit ECC/Parity
Revision 0.9
June. 2001
Rev. 0.9 June. 2001
M383L3313BT1
Revision History
Revision 0 (Aug 1998)
1. First release for internal usage
184pin Registered DDR SDRAM MODULE
Revision 0.1 (May. 1999)
1. Changed die revision from B-die to C-die
2. Changed DC/AC characteristics item from old version.
Revision 0.2 (Aug. 1999)
1. Changed die revision from C-die to B-die
2. Modified binning policy
From
To
-Z (133Mhz)
-Z (133Mhz/266Mbps@CL=2)
-8 (125Mhz)
-Y (133Mhz/266Mbps@CL=2.5)
-0 (100Mhz)
-0 (100Mhz/200Mbps@CL=2)
3.Modified the following AC spec values
From.
-Z
tAC
tDQSCK
tDQSQ
tDS/tDH
tCDLR
*1
tPRE
*1
tRPST
*1
tHZQ
*1
*1
To.
-0
+/- 1ns
+/- 1ns
+/- 0.75ns
0.75 ns
-Z
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
1tCK
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
-Y
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
1tCK
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
-0
+/- 0.8ns
+/- 0.8ns
+/- 0.6ns
0.6 ns
1tCK
0.9/1.1 tCK
0.4/0.6 tCK
+/-0.8ns
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
2.5tCK-tDQSS
1tCK +/- 0.75ns
tCK/2 +/- 0.75ns
tCK/2 +/- 0.75ns
2.5tCK-tDQSS
1tCK +/- 1ns
tCK/2 +/- 1ns
tCK/2 +/- 1ns
: Changed description method for the same functionality. This means no difference from the previous version.
4.Changed the following AC parameter symbol From tDQCK To tAC
Output data access time from CK/CK
Revision 0.3 (Sept. 1999)
1. Changed the odering information.
1-1. Exclude KM mark.
From
KMM383...
1-2. PCB Revison
From
- Blank: 1st generation
-A
: 2nd generation
-B
: 2nd generation
Example:KMM383L3313BT
1-3. Modified binning policy
From
- 0 (100Mhz/200Mbps@CL=2)
- Z (133Mhz/266Mbps@CL=2)
- Y (133Mhz/266Mbps@CL=2.5)
To
M383.....
To
- 0: 1st gernation
- 1: 2nd generation
- 2: 3nd generation
M383L3313BT0
To
- A0 (100Mhz/200Mbps@CL=2)
- A2 (133Mhz/266Mbps@CL=2)
- B0 (133Mhz/266Mbps@CL=2.5)
Rev. 0.9 June. 2001
M383L3313BT1
Revision 0.4 (December. 1999)
184pin Registered DDR SDRAM MODULE
1. Changed from 3.3V to 2.5V in VDDSPD power.
Revision 0.5 (April. 2000)
< Page 3 >
1. Changed pin 90 from WP to NC in pin configuration table.
2. Removed WP in pin description.
< Page 4>
3. Changed bypassing to reflect common Vdd/Vddq plane.
4. Added A12, BA1.
5. Removed WP from serial PD.
< Page 5>
6.
Changed Power & DC operating condition.
Parameter
I/O Reference voltage
Input logic high voltage
Input logic low voltage
Input leakage current
Output High Current (V
OUT
= 1.95V)
Output Low Current (V
OUT
= 0.35V)
Symbol
Min
V
REF
V
IH
(DC)
V
IL
(DC)
I
I
I
OH
I
OL
1.15
From
Max
1.35
V
DDQ
+0.3
V
REF
-0.18
5
To
Min
0.49*VDDQ
V
REF
+0.15
-0.3
-2
-16.8
16.8
Max
0.51*VDDQ
V
DDQ
+0.3
V
REF
-0.15
2
V
REF
+0.18
-0.3
-5
-15.2
15.2
< Page 6 >
7. Added Overshoot/Undershoot spec
. Vih(max) = 4.2V, the overshoot voltage duration is
≤
3ns at VDD.
. Vil(min) =- 1.5V, the overshoot voltage duration is
≤
3ns at VSS.
< Page 6,7 >
8. Changed AC operating conditions as follows.
Parameter/Condition
Symbol
Min
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC)
Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC)
Input Differential Voltage, CK and CK inputs
VID(AC)
0.7
VREF + 0.35
VREF - 0.35
VDDQ+0.6
0.62
From
Max
Min
VREF + 0.31
VREF - 0.31
VDDQ+0.6
To
Max
< page 8, 9>
9. Changed AC parameters as follows.
Parameter
tDQSQ
tDV
from
+/- 0.5(PC266), +/- 0.6(PC200)
+/- 0.35tCK
to
+0.5(PC266), +0.6(PC200)
-
Removed
Comments
Rev. 0.9 June. 2001
M383L3313BT1
10. Added AC parameters as follows
184pin Registered DDR SDRAM MODULE
-A2(PC266@CL=2)
-B0(PC266@CL=2.5)
Min
tHPmin
-0.75ns
tCLmin
or
tCHmin
0.9
0.4
Max
-
-A0(PC200@CL=2)
Min
tHPmin
-1.0ns
tCLmin
or
tCHmin
0.9
0.4
Max
-
Parameter
Symbol
Min
Max
-
tHPmin
-0.75ns
tCLmin
or
tCHmin
0.9
0.4
Output DQS valid window
tQH
Clock half period
QFC setup to first DQS edge on reads
QFC hold after last DQS edge on reads
Write command to QFC delay on write
Write burst end to QFC delay on write
Write burst end to QFC delay on write inter-
rupted by Precharge
tHP
tQCS
tDQCH
tQCSW
tQCHW
tQCHWI
-
-
-
1.1
0.6
4.0
1.1
0.6
4.0
1.1
0.6
4.0
1.25ns
1.25ns
0.5tCK
1.5tCK
1.25ns
1.25ns
0.5tCK
1.5tCK
1.25ns
1.25ns
0.5tCK
1.5tCK
Revision 0.6 (June. 2000)
1. Changed PCB version from T0 to T1.
Revision 0.7 (October. 2000)
1.Added DC target spec values.
2.Deleted tDAL in AC parameter X.
Revision 0.8 (November. 2000)
1.Changed component placement on module PCB in package dimesions.
Revision 0.9 (June. 2001)
1. Changed module current speificaton
2. Changed typo size on module PCB in package dimesions. (from 2.6mm to 3mm).
3. Changed AC parameter table.
Rev. 0.9 June. 2001
M383L3313BT1
184pin Registered DDR SDRAM MODULE
M383L3313BT1 DDR SDRAM 184pin DIMM
32Mx72 DDR SDRAM 184pin DIMM based on 16Mx8
GENERAL DESCRIPTION
The Samsung M383L3313BT1 is 32M bit x 72 Double Data
Rate SDRAM high density memory modules based on first
generation of 128Mb DDR SDRAM respectively. The Samsung
M383L3313BT1 consists of eighteen CMOS 16M x 8 bit with
4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil)
packages, mounted on a 184pin glass-epoxy substrate. Four
0.1uF decoupling capacitors are mounted on the printed circuit
board in parallel for each DDR SDRAM. The M383L3313BT1
is Dual In-line Memory Modules and intended for mounting into
184pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
FEATURE
• Performance range
Part No.
Max Freq.
Interface
SSTL_2
M383L3313BT1-C(L)A2 133MHz(7.5ns@CL=2)
M383L3313BT1-C(L)B0 133MHz(7.5ns@CL=2.5)
M383L3313BT1-C(L)A0 100MHz(10ns@CL=2)
• Power supply : Vdd: 2.5V
±
0.2V, Vddq: 2.5V
±
0.2V
•
Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 15.6us refresh interval(4K/64ms refresh)
• Serial presence detect with EEPROM
• PCB :
Height 1700 (mil),
double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin
Front
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Front
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
*/CS2
DQ48
DQ49
VSS
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
*A13
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
*A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Back
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
/CK0
VSS
DM8
A10
CB6
VDDQ
CB7
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Back
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5
VSS
DQ46
DQ47
*/CS3
VDDQ
DQ52
DQ53
NC
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
VREF
1
DQ0
2
VSS
3
DQ1
4
DQS0
5
DQ2
6
VDD
7
DQ3
8
NC
9
10 /RESET
VSS
11
DQ8
12
DQ9
13
DQS1
14
15 VDDQ
16
*CK1
17
*/CK1
18
VSS
19 DQ10
20 DQ11
21 CKE0
22 VDDQ
23 DQ16
24 DQ17
25 DQS2
26
VSS
27
A9
28 DQ18
29
A7
30 VDDQ
31 DQ19
PIN DESCRIPTION
Pin Name
A0 ~ A11
BA0 ~ BA1
DQ0 ~ DQ63
CB0 ~ CB7
DQS0 ~ DQS8
CK0,CK0
CKE0,CKE1
CS0, CS1
RAS
CAS
WE
DM0 ~ DM8
VDD
VDDQ
VSS
VREF
VDDSPD
SDA
SCL
SA0 ~ 2
VDDID
RESET
NC
Function
Address input (Multiplexed)
Bank Select Address
Data input/output
Check bit(Data-in/data-out)
Data Strobe input/output
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
Data - in mask
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
Power supply for reference
Serial EEPROM Power
Supply
( 2.3V to 3.6V )
Supply
Serial data I/O
Serial clock
Address in EEPROM
VDD identification flag
Reset enable
No connection
*/CK2
*CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
KEY
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
KEY
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
* These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.9 June. 2001
