M464S1654CTS
M464S1654CTS SDRAM SODIMM
PC133/PC100 SODIMM
16Mx64 SDRAM SODIMM based on 16Mx16, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
The Samsung M464S1654CTS is a 16M bit x 64 Synchro-
nous Dynamic RAM high density memory module. The Sam-
sung M464S1654CTS consists of four CMOS 16M x 16 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and
a 2K EEPROM in 8-pin TSSOP package on a 144-pin glass-
epoxy substrate. Three 0.1uF decoupling capacitors are
mounted on the printed circuit board in parallel for each
SDRAM. The M464S1654CTS is a Small Outline Dual In-line
Memory Module and is intended for mounting into 144-pin
edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies allows the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
•
•
•
•
•
FEATURE
• Performance range
Part No.
M464S1654CTS-L7C/C7C
M464S1654CTS-L7A/C7A
M464S1654CTS-L1H/C1H
M464S1654CTS-L1L/C1L
Max Freq. (Speed)
133MHz@CL=2
133MHz@CL=3
100MHz@CL=2
100MHz@CL=3
Burst mode operation
Auto & self refresh capability (8192 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V
±
0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB :
Height (1,000mil),
double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Front
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
V
SS
DQM0
DQM1
V
DD
A0
A1
A2
V
SS
DQ8
DQ9
DQ10
DQ11
V
DD
DQ12
DQ13
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Back
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
V
SS
DQM4
DQM5
V
DD
A3
A4
A5
V
SS
DQ40
DQ41
DQ42
DQ43
V
DD
DQ44
DQ45
Pin
51
53
55
57
59
Front
DQ14
DQ15
V
SS
NC
NC
Pin
52
54
56
58
60
Back
DQ46
DQ47
V
SS
NC
NC
Pin
Front
DQ21
DQ22
DQ23
V
DD
A6
A8
V
SS
A9
A10/AP
V
DD
DQM2
DQM3
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
**SDA
V
DD
Pin
Back
95
97
99
101
103
105
Voltage Key
107
109
CLK0 62 CKE0 111
V
DD
64
V
DD
113
RAS
66
CAS 115
WE
68 *CKE1 117
CS0
70
A12 119
*CS1 72
*A13 121
DU
74 *CLK1 123
V
SS
76
V
SS
125
NC
78
NC
127
NC
80
NC
129
V
DD
82
V
DD
131
DQ16 84 DQ48 133
DQ17 86 DQ49 135
DQ18 88 DQ50 137
DQ19 90 DQ51 139
V
SS
92
V
SS
141
DQ20 94 DQ52 143
96 DQ53
98 DQ54
100 DQ55
102 V
DD
104
A7
106 BA0
108 V
SS
110 BA1
112 A11
114 V
DD
116 DQM6
118 DQM7
120 V
SS
122 DQ56
124 DQ57
126 DQ58
128 DQ59
130 V
DD
132 DQ60
134 DQ61
136 DQ62
138 DQ63
140 V
SS
142 **SCL
144 V
DD
PIN NAMES
Pin Name
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
CLK0
CKE0
CS0
RAS
CAS
WE
DQM0 ~ 7
V
DD
V
SS
SDA
SCL
DU
NC
Function
Address input (Multiplexed)
Select bank
Data input/output
Clock input
Clock enable input
Chip select input
Row address storbe
Column address strobe
Write enable
DQM
Power supply (3.3V)
Ground
Serial data I/O
Serial clock
Don′t use
No connection
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
* These pins are not used in this module.
**
These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 Sept. 2001
M464S1654CTS
PIN CONFIGURATION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
PC133/PC100 SODIMM
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+t
SS
prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA8
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A12
Address
BA0 ~ BA1
RAS
Bank select address
Row address strobe
CAS
Column address strobe
WE
Write enable
DQM0 ~ 7
D Q
0
~
63
Data input/output mask
Data input/output
Power supply/ground
V
DD
/V
SS
Rev. 0.1 Sept. 2001
M464S1654CTS
FUNCTIONAL BLOCK DIAGRAM
CS0
DQM0
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM4
PC133/PC100 SODIMM
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
U0
U2
DQM2
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
DQM6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Serial PD
SCL
47KΩ
WP
SA0 SA1 SA2
SDA
CS
U1
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM7
U3
DQM3
A0 ~ A12, BA0 & 1
RAS
CAS
WE
CKE0
10Ω
DQn
SDRAM U0 ~ U3
SDRAM U0 ~ U3
SDRAM U0 ~ U3
SDRAM U0 ~ U3
SDRAM U0 ~ U3
Every DQ pin of SDRAM
U0
CLK0
U1
U2
U3
V
DD
Three 0.1uF X7R 0603 Capacitors
per each SDRAM
Vss
To all SDRAMs
CLK1
10Ω
10pF
Rev. 0.1 Sept. 2001
M464S1654CTS
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
I N
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
PC133/PC100 SODIMM
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
4
50
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70°C)
Parameter
Supply voltage
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Symbol
V
DD
V
IH
V
IL
V
O H
V
OL
I
LI
Min
3.0
2.0
-0.3
2.4
-
-10
Typ
3.3
3.0
0
-
-
-
Max
3.6
V
DDQ
+0.3
0.8
-
0.4
10
Unit
V
V
V
V
V
uA
1
2
I
OH
= -2mA
I
OL
= 2mA
3
Note
Notes :
1. V
I H
(max) = 5.6V AC.The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(V
DD
= 3.3V, T
A
= 23°C, f = 1MHz, V
REF
= 1.4V
±
200 mV)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN6
C
OUT
Min
25
25
15
15
15
10
13
Max
45
45
25
21
25
12
18
Unit
pF
pF
pF
pF
pF
pF
pF
Parameter
Input capacitance (A
0
~ A
12
, BA0 ~ BA1)
Input capacitance (RAS , CAS, WE)
Input capacitance (CKE0 ~ CKE1)
Input capacitance (CLK0 ~ CLK1)
Input capacitance (CS0 ~ CS1)
Input capacitance (DQM0 ~ DQM7)
Data input/output capacitance (DQ0 ~ DQ63)
Rev. 0.1 Sept. 2001
M464S1654CTS
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70° C)
Parameter
Symbol
Burst length = 1
t
RC
≥
t
RC
(min)
I
O
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
I H
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
I H
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
O
= 0 mA
Page burst
4banks Activated.
t
CCD
= 2CLKs
t
RC
≥
t
RC
(min)
CKE
≤
0.2V
C
L
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(V
I H
/V
IL
=V
DDQ
/V
SSQ
).
Test Condition
PC133/PC100 SODIMM
Version
-7C
-7A
400
-1H
400
-1L
400
Unit
Note
Operating current
(One bank active)
Precharge standby cur-
rent in power-down mode
I
CC1
440
mA
1
I
CC2
P
I
C C 2
PS
I
CC2
N
8
8
80
mA
Precharge standby cur-
rent in non power-down
mode
mA
40
24
24
120
mA
I
CC2
NS
I
CC3
P
I
C C 3
PS
I
CC3
N
Active standby current in
power-down mode
mA
Active standby current in
non power-down mode
(One bank active)
I
CC3
NS
100
mA
Operating current
(Burst mode)
I
CC4
560
560
520
520
mA
1
Refresh current
Self refresh current
I
CC5
I
CC6
880
800
12
6
760
760
mA
mA
mA
2
Rev. 0.1 Sept. 2001
