M48Z129Y*
M48Z129V
5.0V OR 3.3V, 1 Mbit (128 Kb x 8) ZEROPOWER
®
SRAM
FEATURES SUMMARY
■
■
■
■
■
■
■
■
■
INTEGRATED, ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, AND
BATTERY
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
10 YEARS OF DATA RETENTION IN THE
ABSENCE OF POWER
MICROPROCESSOR POWER-ON RESET
(RESET VALID EVEN DURING BATTERY
BACK-UP MODE)
BATTERY LOW PIN - PROVIDES WARNING
OF BATTERY END-OF-LIFE
AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECTION
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
– M48Z129Y: V
CC
= 4.5 to 5.5V
4.2V
≤
V
PFD
≤
4.5V
– M48Z129V: V
CC
= 3.0 to 3.6V
2.7V
≤
V
PFD
≤
3.0V
SELF-CONTAINED BATTERY IN THE
CAPHAT™ DIP PACKAGE
PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 128K x 8 SRAMs
Figure 1. 32-pin PMDIP Module
32
1
PMDIP32 (PM)
Module
* Contact local ST sales office for availability.
March 2005
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M48Z129Y*, M48Z129V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 32-pin PMDIP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2.
Table 1.
Figure 3.
Figure 4.
Logic Diagram . .
Signal Names . .
DIP Connections
Block Diagram . .
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.....4
.....4
.....4
.....5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Address Controlled, READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms . . . . . . . . . . . . . 6
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. WRITE Enable Controlled, WRITE Mode AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 8. Chip Enable Controlled, WRITE Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
V
CC
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 10.
Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12.PMDIP32 – 32-pin Plastic Module DIP, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 11. PMDIP32 – 32-pin Plastic DIP, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . 13
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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M48Z129Y*, M48Z129V
Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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M48Z129Y*, M48Z129V
SUMMARY DESCRIPTION
The M48Z129Y/V ZEROPOWER
®
SRAM is a
1,048,576 bit non-volatile static RAM organized as
131,072 words by 8 bits. The device combines an
internal lithium battery, a CMOS SRAM and a con-
trol circuit in a plastic 32-pin DIP Module. The
M48Z129Y/V directly replaces industry standard
128K x 8 SRAM. It also provides the non-volatility
of FLASH without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed.
Figure 2. Logic Diagram
VCC
Table 1. Signal Names
A0-A16
DQ0-DQ7
Address Inputs
Data Inputs / Outputs
Chip Enable
Output Enable
WRITE Enable
Reset Output (Open Drain)
Battery Low Output (Open Drain)
Supply Voltage
Ground
17
A0-A16
W
E
G
M48Z129Y
M48Z129V
8
DQ0-DQ7
E
G
RST
BL
W
RST
BL
V
CC
VSS
AI02309
V
SS
Figure 3. DIP Connections
RST
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
32
2
31
3
30
4
29
28
5
27
6
7
26
8 M48Z129Y 25
9 M48Z129V 24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
AI02310
VCC
A15
BL
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
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M48Z129Y*, M48Z129V
Figure 4. Block Diagram
VCC
A0-A16
POWER
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
131,072 x 8
SRAM ARRAY
DQ0-DQ7
E
W
G
INTERNAL
BATTERY
RST
BL
VSS
AI03608
OPERATION MODES
The M48Z129Y/V also has its own Power-Fail De-
tect circuit. This control circuitry constantly moni-
tors the supply voltage for an out of tolerance
condition. When V
CC
is out of tolerance, the circuit
write protects the SRAM, providing data security in
Table 2. Operating Modes
Mode
Deselect
WRITE
READ
READ
Deselect
Deselect
V
SO
to V
PFD
(min)
(1)
≤
V
SO(1)
4.5 to 5.5V
or
3.0to 3.6V
V
CC
E
V
IH
V
IL
V
IL
V
IL
X
X
G
X
X
V
IL
V
IH
X
X
W
X
V
IL
V
IH
V
IH
X
X
DQ0-DQ7
High Z
D
IN
D
OUT
High Z
High Z
High Z
Power
Standby
Active
Active
Active
CMOS Standby
Battery Back-up Mode
the midst of unpredictable system operation. As
V
CC
falls, the control circuitry automatically switch-
es to the battery, maintaining data until valid power
is restored.
Note: X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
1. See
Table 10., page 12
for details.
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