M50FW002
2 Mbit (256Kb x8, Boot Block)
3V Supply Firmware Hub Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY
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SUPPLY VOLTAGE
– V
CC
= 3 V to 3.6 V for Program, Erase and
Read Operations
– V
PP
= 12 V for Fast Program and Fast Erase
(optional)
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Figure 1. Packages
TWO INTERFACES
– Firmware Hub (FWH) Interface for embedded
operation with PC Chipsets
– Address/Address Multiplexed (A/A Mux)
Interface for programming equipment
compatibility
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FIRMWARE HUB (FWH) HARDWARE
INTERFACE MODE
– 5 Signal Communication Interface supporting
Read and Write Operations
– Hardware Write Protect Pins for Block
Protection
– Register Based Read and Write Protection
– 5 Additional General Purpose Inputs for
platform design flexibility
– Synchronized with 33MHz PCI clock
– Multi-byte Read Operation (1-byte, 16-byte,
32-byte)
PLCC32 (K)
s
PROGRAMMING TIME
– 10 µs typical
– Quadruple Byte Programming Option
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ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 29h
s
7
MEMORY BLOCKS
– 1 Boot Block (Top Location)
– 4 Main Blocks and 2 Parameter Blocks
s
PROGRAM/ERASE CONTROLLER
– Embedded Byte Program, Block Erase and
Chip Erase algorithms
– Status Register Bits
s
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PROGRAM and ERASE SUSPEND
FOR USE in PC BIOS APPLICATIONS
May 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M50FW002
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Firmware Hub (FWH) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Firmware Hub (FWH) Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
FWH Bus Read Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
FWH Bus Write Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
A/A Mux Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Manufacturer and Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 17
Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Firmware Hub (FWH) General Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Firmware Hub Register Configuration Map
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Lock Register Bit Definitions
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
General Purpose Input Register Definition
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC Measurement Conditions (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC Measurement Conditions (A/A Mux Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Device Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clock Characteristics (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC Signal Timing Characteristics (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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M50FW002
Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Read AC Characteristics (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Write AC Characteristics (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data . . . . . . . . . . . . . . . . . 36
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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M50FW002
SUMMARY DESCRIPTION
The M50FW002 is a 2 Mbit (256Kb x8) non-vola-
tile memory that can be read, erased and repro-
grammed. These operations can be performed
using a single low voltage (3.0 to 3.6V) supply. For
fast programming and fast erasing in production
lines an optional 12V power supply can be used to
reduce the programming and the erasing times.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental Pro-
gram or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
Figure 2. PLCC Connections
A8
A9
RP
VPP
VCC
RC
A10
The device features an asymmetrical blocked ar-
chitecture. The device has an array of 7 blocks:
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1 Boot Block of 16 KByte
s
2 Parameter Blocks of 8 KByte each
s
1 Main Block of 32 KByte
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3 Main Blocks of 64 KByte each
Two different bus interfaces are supported by the
memory. The primary interface, the Firmware Hub
(or FWH) Interface, uses Intel’s proprietary FWH
protocol. This has been designed to remove the
need for the ISA bus in current PC Chipsets; the
M50FW002 acts as the PC BIOS on the Low Pin
Count bus for these PC Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is delivered with all the bits erased
(set to 1).
A/A Mux
A/A Mux
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
FGPI2
FGPI3
RP
VPP
VCC
CLK
FGPI4
1 32
FGPI1
FGPI0
WP
TBL
ID3
ID2
ID1
ID0
FWH0
IC (VIL)
NC
NC
VSS
VCC
INIT
FWH4
RFU
RFU
IC (VIH)
NC
NC
VSS
VCC
G
W
RB
DQ7
9
M50FW002
25
17
FWH1
FWH2
VSS
FWH3
RFU
RFU
RFU
A/A Mux
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
A/A Mux
AI05749
Note: Pins 27 and 28 are not internally connected.
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M50FW002
Figure 3. Logic Diagram (FWH Interface)
VCC VPP
VCC VPP
4
ID0-ID3
5
FGPI0-
FGPI4
FWH4
CLK
IC
RP
INIT
M50FW002
WP
TBL
RC
IC
G
W
RP
M50FW002
RB
4
FWH0-
FWH3
A0-A10
11
8
DQ0-DQ7
Figure 4. Logic Diagram (A/A Mux Interface)
VSS
AI05747
VSS
AI05748
Table 1. Signal Names (FWH Interface)
FWH0-FWH3
FWH4
ID0-ID3
FGPI0-FGPI4
IC
RP
INIT
CLK
TBL
WP
RFU
V
CC
V
PP
V
SS
NC
Input/Output Communications
Input Communication Frame
Identification Inputs
General Purpose Inputs
Interface Configuration
Interface Reset
CPU Reset
Clock
Top Block Lock
Write Protect
Reserved for Future Use. Leave
disconnected
Supply Voltage
Optional Supply Voltage for Fast
Erase Operations
Ground
Not Connected Internally
Table 2. Signal Names (A/A Mux Interface)
IC
A0-A10
DQ0-DQ7
G
W
RC
RB
RP
V
CC
V
PP
V
SS
NC
Interface Configuration
Address Inputs
Data Inputs/Outputs
Output Enable
Write Enable
Row/Column Address Select
Ready/Busy Output
Interface Reset
Supply Voltage
Optional Supply Voltage for Fast
Program and Fast Erase Operations
Ground
Not Connected Internally
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