19-2654; Rev 2; 12/10
KIT
ATION
EVALU
BLE
AVAILA
58.6ksps, 16-Bit,
2-Wire Serial ADC in a 14-Pin TSSOP
Features
o
High-Speed I
2
C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
o
+4.75V to +5.25V Single Supply
o
+2.7V to +5.5V Adjustable Logic Level
o
Internal +4.096V Reference
o
External Reference: 1V to V
AVDD
o
Internal 4MHz Conversion Clock
o
58.6ksps Sampling Rate
o
AutoShutdown Between Conversions
o
Low Power
5.0mW at 58.6ksps
4.2mW at 50ksps
2.0mW at 10ksps
0.23mW at 1ksps
3µW in Shutdown
o
Small 14-Pin TSSOP Package
General Description
The MAX1169 is a low-power, 16-bit successive-
approximation analog-to-digital converter (ADC). The
device features automatic power-down, an on-chip
4MHz clock, a +4.096V internal reference, and an
I
2
C-compatible 2-wire serial interface capable of both
fast and high-speed modes.
The MAX1169 operates from a single supply and con-
sumes 5mW at the maximum conversion rate of
58.6ksps. AutoShutdown™ powers down the device
between conversions, reducing supply current to less
than 50µA at a 1ksps throughput rate. The option of a
separate digital supply voltage allows direct interfacing
with +2.7V to +5.5V digital logic.
The MAX1169 performs a unipolar conversion on its
single analog input using its internal 4MHz clock. The
full-scale analog input range is determined by the inter-
nal reference or by an externally applied reference volt-
age ranging from 1V to V
AVDD
.
The four address select inputs (ADD0 to ADD3) allow
up to 16 MAX1169 devices on the same bus.
The MAX1169 is packaged in a 14-pin TSSOP and
operates over an extended temperature range. Refer to
the MAX1069 data sheet for a 14-bit device in a pin-
compatible package.
PART
MAX1169
Ordering Information
TEMP RANGE
-40°C to +85°C
PIN-
PACKAGE
14 TSSOP
INL
(LSB)
±2
Applications
Hand-Held Portable Applications
Medical Instruments
Battery-Powered Test Equipment
Solar-Powered Remote Systems
Received-Signal-Strength Indicators
System Supervision
MAX1169BEUD+
+Denotes
a lead(Pb)-free/RoHS-compliant package.
Pin Configuration
TOP VIEW
DGND 1
SCL
SDA
2
3
14 ADD3
13 REF
12 REFADJ
ADD2 4
ADD1 5
ADD0 6
DVDD 7
MAX1169
11 AGNDS
10 AIN
9
8
AGND
AVDD
TSSOP
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
MAX1169
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND.........................................................-0.3V to +6V
DVDD to DGND ........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AGNDS to AGND...................................................-0.3V to +0.3V
AIN, REF, REFADJ to AGND ..................-0.3V to (V
AVDD
+ 0.3V)
SCL, SDA, ADD_ to DGND.......................................-0.3V to +6V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (T
A
= +85°C)
14-Pin TSSOP (derate 9.1mW/°C above +85°C) .........864mW
Operating Temperature Ranges
MAX1169_EUD ................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
AVDD
= +4.75V to +5.25V, V
DVDD
= +2.7V to +5.5V, f
SCL
= 1.7MHz (33% duty cycle), f
SAMPLE
= 58.6ksps, V
REF
= +4.096V, external
reference applied to REF, REFADJ = AVDD, C
REF
= 10µF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
DC ACCURACY
(Note 1)
Resolution
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
Offset-Error Temperature
Coefficient
Gain Error
Gain Temperature Coefficient
DYNAMIC PERFORMANCE (f
IN(sine wave)
= 1kHz, V
IN
= V
REF(P-P)
, f
SAMPLE
= 58.6ksps)
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Signal-to-Noise Ratio
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
(Figure 11)
Conversion Time
(SCL Stretched Low)
Throughput Rate (Note 4)
Internal Clock Frequency
Track/Hold Acquisition Time
Aperture Delay, Figure 11c
(Note 6)
t
CONV
f
SAMPLE
f
CLK
t
ACQ
t
AD
(Note 5)
Fast mode
High-speed mode
1100
50
30
Fast mode
High-speed mode
Fast mode
High-speed mode
4
7.1
5.8
7.5
6
19
58.6
μs
ksps
MHz
ns
ns
SINAD
THD
SFDR
SNR
FPBW
-3dB point
SINAD > 81dB
Up to the 5th harmonic
92
87
86
90
-102
105
90
4
33
-90
dB
dB
dB
dB
MHz
kHz
(Note 3)
INL
DNL
MAX1169B
MAX1169B, no missing codes
16-bit
NMC
0.7
2
1.0
±0.25
0.1
±0.5
16
±2
1.7
5
Bits
LSB
LSB
mV
ppm/°C
%FSR
ppm/°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= +4.75V to +5.25V, V
DVDD
= +2.7V to +5.5V, f
SCL
= 1.7MHz (33% duty cycle), f
SAMPLE
= 58.6ksps, V
REF
= +4.096V, external
reference applied to REF, REFADJ = AVDD, C
REF
= 10µF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
Aperture Jitter, Figure 11c
ANALOG INPUT (AIN)
Input Voltage Range
Input Leakage Current
Input Capacitance
REF Output Voltage
Reference Temperature
Coefficient
Reference Short-Circuit Current
REFADJ Output Voltage
REFADJ Input Range
EXTERNAL REFERENCE (REFADJ = AVDD)
REFADJ Buffer Disable Voltage
REFADJ Buffer Enable Voltage
Reference Input Voltage Range
REF Input Current
I
REF
(Note 7)
V
REF
= +4.096V, V
IN
= V
REF(P-P)
,
f
IN(sine wave)
= 1kHz, f
SAMPLE
= 58.6ksps
V
REF
= +4.096V, shutdown
DIGITAL INPUTS/OUTPUTS (SCL, SDA)
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Current
Input Capacitance
Output Low Voltage
V
IH
V
IL
V
HYST
I
IN
C
IN
V
OL
I
SINK
= 3mA
0.7
V
DVDD
0.3
V
DVDD
0.1
V
DVDD
15
0.4
0.1
V
DVDD
±10
0.7
V
DVDD
0.3
V
DVDD
V
V
V
μA
pF
V
1.0
27
0.1
Pull REFADJ high to disable the internal
bandgap reference and reference buffer
V
AVDD
- 0.1
V
AVDD
- 0.4
V
AVDD
V
V
V
μA
For small adjustments, from 4.096V
C
IN
V
REF
TC
REF
I
REFSC
4.056
T
A
= -40°C to +85°C
4.056
V
AIN
On/off-leakage current, V
AIN
= 0V or V
AVDD
,
no clock, f
SCL
= 0
0
±0.01
35
4.096
±35
10
4.096
±60
4.136
4.136
V
REF
±10
V
μA
pF
V
ppm/°C
mA
V
mV
SYMBOL
t
AJ
Fast mode
High-speed mode
CONDITIONS
MIN
TYP
100
100
MAX
UNITS
ps
MAX1169
INTERNAL REFERENCE (bypass REFADJ with 0.1μF to AGND and REF with 10μF to AGND)
ADDRESS SELECT INPUTS (ADD3, ADD2, ADD1, ADD0)
Input High Voltage
Input Low Voltage
Input Hysteresis
V
V
V
_______________________________________________________________________________________
3
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
MAX1169
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= +4.75V to +5.25V, V
DVDD
= +2.7V to +5.5V, f
SCL
= 1.7MHz (33% duty cycle), f
SAMPLE
= 58.6ksps, V
REF
= +4.096V, external
reference applied to REF, REFADJ = AVDD, C
REF
= 10µF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
Input Current
Input Capacitance
POWER REQUIREMENTS (AVDD, AGND, DVDD, DGND)
Analog Supply Voltage
Digital Supply Voltage
AVDD
DVDD
Internal reference
(powered down
between conversions,
R/W = 0)
f
SAMPLE
= 58.6ksps
f
SAMPLE
= 10ksps
f
SAMPLE
= 1ksps
Shutdown
f
SAMPLE
= 58.6ksps
Analog Supply Current
I
AVDD
Internal reference
(always on, R/W = 1)
f
SAMPLE
= 10ksps
f
SAMPLE
= 1ksps
Shutdown
f
SAMPLE
= 58.6ksps
External reference
(REFADJ = AVDD)
f
SAMPLE
= 58.6ksps
Digital Supply Current
I
DVDD
f
SAMPLE
= 10ksps
f
SAMPLE
= 1ksps
Shutdown
Power-Supply Rejection Ratio
Serial Clock Frequency
Bus Free Time Between a STOP
and a START Condition
Hold Time for Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition (Sr)
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Transmitting
Setup Time for STOP Condition
Capacitive Load for Each Bus
Pulse Width of Spike Suppressed
PSRR
f
SCL
t
BUF
t
HD, STA
t
LOW
t
HIGH
t
SU, STA
t
HD, DAT
t
SU, DAT
t
R
t
F
t
SU, STO
C
B
t
SP
(Note 10)
(Note 10)
(Note 9)
1.3
0.6
1.3
0.6
0.6
0
100
20 + 0.1C
B
20 + 0.1C
B
0.6
300
300
400
50
900
V
AVDD
= 5V ±5%, full-scale input (Note 8)
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE
(Figure 1a and Figure 2)
400
kHz
μs
μs
μs
μs
μs
ns
ns
ns
ns
μs
pF
ns
f
SAMPLE
= 10ksps
f
SAMPLE
= 1ksps
Shutdown
4.75
2.7
1.8
0.7
40
0.4
1.8
1.4
1.1
0.4
0.90
0.36
40
0.4
260
65
6
0.2
5
5
16
LSB/V
5
400
μA
5
1.8
5
2.5
5.25
5.5
2.5
V
V
mA
μA
mA
μA
mA
μA
15
SYMBOL
CONDITIONS
MIN
TYP
MAX
±10
UNITS
μA
pf
4
_______________________________________________________________________________________
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= +4.75V to +5.25V, V
DVDD
= +2.7V to +5.5V, f
SCL
= 1.7MHz (33% duty cycle), f
SAMPLE
= 58.6ksps, V
REF
= +4.096V, external
reference applied to REF, REFADJ = AVDD, C
REF
= 10μF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
Serial Clock Frequency
Hold Time (Repeated) Start
Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
(Current Source Enabled)
Rise Time of SCL Signal After
Acknowledge Bit
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP Condition
Capacitive Load for Each Bus
Pulse Width of Spike Suppressed
SYMBOL
f
SCLH
t
HD, STA
t
LOW
t
HIGH
t
SU, STA
t
HD, DAT
t
SU, DAT
t
RCL
t
RCL1
t
FCL
t
RDA
t
FDA
t
SU, STO
C
B
t
SP
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 10)
(Note 9)
(Note 11)
160
320
120
160
0
10
10
20
20
20
20
160
400
10
80
160
80
160
160
150
CONDITIONS
MIN
TYP
MAX
1.7
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
ns
MAX1169
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE
(Figure 1b and Figure 2)
Note 1:
DC accuracy is tested at V
AVDD
= +5.0V and V
DVDD
= +3.0V. Performance at power-supply tolerance limits is guaranteed
by power-supply rejection test.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3:
Offset nullified.
Note 4:
One sample is achieved every 18 clocks in continuous conversion mode:
⎛
18 clocks
⎞
f
SAMPLE
= ⎜
+
t
CONV
⎟
⎝
f
SCL
⎠
-1
Note 5:
The track/hold acquisition time is two SCL cycles as illustrated in Figure 11:
⎛
1
⎞
t
ACQ
=
2
× ⎜
⎟
⎝
f
SCL
⎠
Note 6:
A filter on SDA and SCL delays the sampling instant and suppresses noise spikes less than 10ns in high-speed mode and
50ns in fast mode.
Note 7:
ADC performance is limited by the converter’s noise floor, typically 225μV
P-P
.
Note 8:
PSRR
=
2
N
⎡
V
FS
(5.25V)-V
FS
(4.75V)
⎤ ×
⎣
⎦
V
REF
5.25V - 4.75V
where N is the number of bits (16).
_______________________________________________________________________________________
5
