dent of the Hold input. When the Hold input is at V+ the
display latch pulse is inhibited, and the display latches
are not updated; when the Hold input is low or at the
Test voltage, the display is updated at the end of each
conversion. The MAX136 maintains low-power dissipa-
tion even during display hold by eliminating the pulldown
resistor between Hold and Test present on the ICL7116.
The Hold input is CMOS compatible, and can also be
driven by a switch connected between Test and V+
(Figure 1).
Unlike the ICL7136, the MAX136 does not have a refer-
ence low input. Apply the reference voltage between
Reference High (REF HI) and
Hold Input
Reference Input
0.47µF
34
33
LCD DISPLAY
C+ REF C- REF
2-19 SEGMENT
22-25 DRIVE
31
IN HI
PDL 20
BACKPLANE
BP 21 MINUS SIGN DRIVE
30
TEST 37
RUN
IN LO
1
32
HOLD
COMMON
HOLD
35
28
V+
BUFF
0.47µF
29
27
0.47µF
34
33
LCD DISPLAY
+ REF C- REF
C
2-19 SEGMENT
22-25 DRIVE
31
IN HI
PDL 20
BACKPLANE
BP 21 MINUS SIGN DRIVE
30
TEST 37
RUN
IN LO
1
32
HOLD
COMMON
HOLD
35
28
V+
BUFF
0.47µF
29
27
1MI
ANALOG
INPUT
0.01µF
1MI
ANALOG
INPUT
0.01µF
180kI
MAX136
A/Z
INT
REF HI
V-
OSC
1
150kI
V
REF
36
26
TO ANALOG
COMMON (P32)
9V
100kI
180kI
MAX136
A/Z
INT
REF HI
V-
OSC
1
150kI
V
REF
36
26
TO ANALOG
COMMON (P32)
9V
100kI
0.047µF
0.047µF
OSC
2
OSC
3
39
38 C
OSC
40
R
OSC
50pF
180kI
OSC
2
OSC
3
39
38 C
OSC
40
R
OSC
50pF
180kI
Figure 1. MAX136 Typical Operating Circuit, 200mV Full Scale
Figure 2. MAX136 Typical Operating Circuit, 2.0V Full Scale
Maxim Integrated
3
MAX136
Low Power, 3
1
⁄
2
Digit A/D Converter
with Display Hold
Pin Configurations (continued)
TOP VIEW
REF HI
HOLD
OSC1
OSC2
OSC3
TEST
N.C.
6
5
4
3
2
1
44 43 42 41 40
44
43
42
41
40
39
38
37
36
35
F1
G1
E1
D2
C2
N.C.
B2
A2
F2
E2
D3
7
8
9
10
11
12
13
14
15
16
17
18
19 20 21 22 23 24 25 26 27 28
39
V+
38
C+REF
37
C-REF
36
COMMON
35
IN HI
34
REF HI
V+
C+REF
C-REF
COMMON
INHI
INLO
A/Z
BUFF
INT
V-
C1
D1
A1
B1
N.C.
N.C.
TEST
OSC3
N.C.
OSC2
OSC1
HOLD
D1
C1
B1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
N.C.
G2(TENS)
C3
A3
G3
BP
POL(-)
AB4
E3
F3
B3
MAX136
34
N.C.
33
IN LO
32
A/Z
31
BUFF
30
INT
29
V−
MAX136
AB4
POL
N.C.
BP
G3
A3
F3
C3
PLCC
G2
B3
E3
For the latest package outline information and land patterns (footprints), go to
www.maximintegrated.com/packages.
Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PART TYPE
40 PDIP
44 PLCC
44 MQFP
PACKAGE CODE
P40+1
Q44+1
M44+5
DOCUMENT NO.
21-0044
21-0049
21-0826
LAND PATTERN No.
—
90-0236
90-0169
4
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
MQFP
Package Information
Maxim Integrated
MAX136
Low Power, 3
1
⁄
2
Digit A/D Converter
with Display Hold
Revision History
REVISION
NUMBER
0
1
REVISION
DATE
2/87
11/12
Initial release
Add MQFP package to
Ordering Information
and
Package Information.
DESCRIPTION
PAGES
CHANGED
—
1, 4
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
