Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V
DD
= +5V, V
SS
= 0V, V
CM
= 0V, V
OUT
= V
DD
/2, R
L
≥ 1MΩ connected to V
DD
/2,
SHDN
= V
DD
(MAX4481 only),
T
A
= +25°C,
unless
otherwise noted.)
PARAMETER
Supply Voltage Range
Supply Current per Amplifier
Supply Current in Shutdown
Input Offset Voltage
Input Bias Current
Input Offset Current
Input Resistance
Input Common-Mode Voltage
Range
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
Large-Signal Voltage Gain
SYMBOL
V
DD
I
DD
I
SHDN
V
OS
I
B
I
OS
R
IN
V
CM
CMRR
PSRR
A
VOL
(Note 1)
(Note 1)
Differential or common mode
Inferred from CMRR test
V
SS
≤ V
CM
≤ V
DD
- 1.3V
2.5V ≤ V
DD
≤ 5.5V
V
SS
+ 0.02V ≤ V
OUT
≤ V
DD
- 0.03V
V
SS
+ 0.10V ≤ V
OUT
≤ V
DD
- 0.20V
Specified as
V
DD
- V
OUT
Specified as
V
OUT
- V
SS
Sourcing
Sinking
Device in shutdown mode,
SHDN
= V
SS
,
V
SS
< V
OUT
< V
CC
(MAX4481 only)
MAX4481 only
MAX4481 only
SHDN
= V
DD
or V
SS
(MAX4481 only)
0.7 x V
DD
±0.001
±1
140
±500
R
L
= 100kΩ
R
L
= 5kΩ
R
L
= 100kΩ
R
L
= 5kΩ
R
L
= 100kΩ
R
L
= 5kΩ
94
V
SS
71
82
86
92
110
105
4
80
1
8
3
17
±0.01
±0.1
0.3 x V
DD
30
150
dB
V
DD
= 2.5V
V
DD
= 5.0V
SHDN
= V
SS
(MAX4481 only)
CONDITIONS
Inferred from PSRR test
MIN
2.5
45
50
0.05
±1
±0.1
±0.1
1000
V
DD
-
1.3
100
0.5
±5.5
±100
±100
TYP
MAX
5.5
UNITS
V
μA
μA
mV
pA
pA
MΩ
V
dB
dB
Output Voltage High
Output Voltage Low
Output Short-Circuit Current
Shutdown Mode Output Leakage
SHDN
Logic Low
SHDN
Logic High
SHDN
Input Current
Gain-Bandwidth Product
V
OH
V
OL
I
SC
I
OUTSHDN
V
IL
V
IH
I
IL
, I
IH
GBW
mV
mV
mA
μA
V
V
nA
kHz
www.maximintegrated.com
Maxim Integrated │
2
MAX4480–MAX4483
Electrical Characteristics (continued)
PARAMETER
Phase Margin
Gain Margin
Slew Rate
Input Voltage Noise Density
Input Current Noise Density
Capacitive-Load Stability
Shutdown Delay Time
Enable Delay Time
Power-On Time
Input Capacitance
Total Harmonic Distortion
Settling Time to 0.1%
SR
e
n
i
n
C
LOAD
t
SHDN
t
EN
t
ON
C
IN
THD
t
S
f = 10kHz
f = 10kHz
A
V
= +1V/V
SYMBOL
φM
Single/Dual/Quad, Low-Cost, Single-Supply,
Rail-to-Rail Op Amps with Shutdown
(V
DD
= +5V, V
SS
= 0V, V
CM
= 0V, V
OUT
= V
DD
/2, R
L
≥ 1MΩ connected to V
DD
/2,
SHDN
= V
DD
(MAX4481 only),
T
A
= +25°C,
unless
otherwise noted.)
CONDITIONS
MIN
TYP
70
30
80
100
1
400
0.4
12
15
2.0
f = 1kHz, V
OUT
=
2V
P-P
, A
V
= +1V/V
V
OUT
= 2V step
R
L
= 100kΩ
0.005
50
MAX
UNITS
degrees
dB
V/ms
nV/√Hz
nV/√Hz
pF
μs
μs
μs
pF
%
μs
MAX4481 only
MAX4481 only
Electrical Characteristics
PARAMETER
Supply Voltage Range
Supply Current per Amplifier
Supply Current in Shutdown
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Input Common-Mode Voltage
Range
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
Shutdown Mode Output Leakage
SHDN
Logic Low
SHDN
Logic High
SHDN
Input Current
Large-Signal Voltage Gain
Output Voltage High
Output Voltage Low
(V
DD
= +5V, V
SS
= 0V, V
CM
= 0V, V
OUT
= V
DD
/2, R
L
≥ 1MΩ connected to V
DD
/2,
SHDN
= V
DD
(MAX4481 only),
TA = -40°C to +125°C,
unless otherwise noted.)
SYMBOL
V
DD
I
DD
I
SHDN
V
OS
TCV
OS
I
B
I
OS
V
CM
CMRR
PSRR
(Note 1)
(Note 1)
Inferred from CMRR test
V
SS
≤ V
CM
≤ V
DD
- 1.4V
2.5V ≤ V
DD
≤ 5.5V
-40°C to +85°C
+85°C to +125°C
V
SS
67
77
±0.5
μA
±2.5
0.3 x V
DD
0.7 x V
DD
1
84
200
50
V
V
µA
dB
mV
mV
±3
±100
±100
V
DD
-
1.4
SHDN
= V
SS
(MAX4481 only)
CONDITIONS
Inferred from PSRR test
MIN
2.5
TYP
MAX
5.5
120
1.0
9
UNITS
V
μA
μA
mV
μV/°C
pA
pA
V
dB
dB
Device in shutdown
mode,
SHDN
= V
SS
,
I
OUTSHDN
V
SS
< V
OUT
< V
CC
(MAX4481 only)
V
IL
V
IH
I
IL
, I
IH
A
VOL
V
OH
V
OL
MAX4481 only
MAX4481 only
SHDN
= V
DD
or V
SS
(MAX4481 only)
V
SS
+ 0.1V ≤ V
OUT
≤ V
DD
- 0.20V, R
L
= 5kΩ
Specified as V
DD
- V
OUT
, R
L
= 5kΩ
Specified as V
OUT
- VSS, R
L
= 5kΩ
Note 1:
Guaranteed by design.
Note 2:
Specifications are 100% tested at T
A
= +25°C (exceptions noted). All temperature limits are guaranteed by design.
