Operating Temperature Range ......................... -40°C to +105°C
Storage Temperature Range ............................ -65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) ................................. +300°C
Soldering Temperature (reflow) .......................................+260°C
Package Thermal Characteristics
TQFN
Junction-to-Ambient Thermal Resistance (θ
JA
) ........+29°C/W
Junction-to-Case Thermal Resistance (θ
JC
) ............+1.7°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V
AGND
= 32V to 60V, V
EE
= V
DGND
= 0V, T
A
= -40°C to +105°C. All voltages are referenced to V
EE
, unless otherwise noted. Typical
values are at V
AGND
= 54V, T
A
= +25°C, and default register settings. Currents are positive when entering the pin, and negative
otherwise.) (Note 2)
PARAMETER
POWER SUPPLIES
Operating Voltage Range
V
AGND
I
EE
V
AGND
- V
EE
V
OUT_
= V
SENSE_
= V
EE
;
INT,
SDAOUT,
and all logic inputs unconnected;
V
SCL
= V
SDAIN
= V
DD
; measured at AGND
in power mode after GATE_ pullup
Power mode, gate drive on, V
GATE_
= V
EE
Port SHDN mode enabled;
V
GATE_
= V
EE
+ 10V
V
SENSE_
= 500mV, V
GATE_
= V
EE
+ 2V
V
GATE_
- V
EE
, power mode, gate-drive on
I
LIM_
register
set to 80h,
Class 0–3
8.5
-40
32
60
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Currents
5
7
mA
GATE DRIVER AND CLAMPING
GATE_ Pullup Current
GATE_ Pulldown Current
Strong Pulldown Current
External Gate Drive
I
PU
I
PDW
I
PDS
V
GS
-50
40
25
9.5
10.5
-60
µA
µA
mA
V
CURRENT LIMIT AND OVERCURRENT
101
106.25
111.5
Current-Limit Clamp Voltage
V
SU_LIM
Maximum V
SENSE_
allowed during
I
LIM_
register
current-limit
set to C0h,
conditions,
Class 4
V
OUT_
= 0V (Note 3)
I
LIM_
register
set to C0h,
Class 5
200
212.5
225
mV
405
430
455
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Maxim Integrated
│
2
MAX5980A
Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
Electrical Characteristics (continued)
(V
AGND
= 32V to 60V, V
EE
= V
DGND
= 0V, T
A
= -40°C to +105°C. All voltages are referenced to V
EE
, unless otherwise noted. Typical
values are at V
AGND
= 54V, T
A
= +25°C, and default register settings. Currents are positive when entering the pin, and negative
otherwise.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
I
CUT_
register
set to 14h,
Class 0 and 3
I
CUT_
register
set to 22h,
Class 4
I
CUT_
register
set to 22h,
Class 5
I
LIM
register
set to 80h
I
LIM
register
set to C0h
MIN
89
TYP
93.75
MAX
98.5
UNITS
Overcurrent Threshold after
Startup
V
CUT
Overcurrent V
SENSE_
threshold allowed for
t ≤ t
FAULT
after startup,
V
OUT_
= 0V
151
159
167
mV
303
319
32
335
Foldback Initial Voltage
V
FLBK_ST
V
AGND
- V
OUT_
above
which the current-limit trip
voltage starts folding back
V
18
46
35
-2
29
3
62
1
V
mV
µA
V
V
V
V
V
3.6
V
V
°C
°C
2
-70
0.7
1.5
1
2.0
1.25
2.5
µA
MΩ
V
Foldback Final Voltage
Minimum Foldback Current-Limit
Threshold
SENSE_ Input Bias Current
SUPPLY MONITORS
V
EE
Undervoltage Lockout
V
EE
Undervoltage Lockout
Hysteresis
V
EE
Overvoltage Lockout
V
EE
Overvoltage-Lockout
Hysteresis
V
EE
Undervoltage
V
DD
Output Voltage
V
DD
Undervoltage Lockout
Thermal-Shutdown Threshold
Thermal-Shutdown Hysteresis
OUTPUT MONITOR
OUT_ Input Current
Idle Pullup Resistance at OUT_
PGOOD High Threshold
V
FLBK_END
V
TH_FB
V
AGND
- V
OUT_
above which the current
limit reaches V
TH_FB
V
OUT_
= V
AGND
= 60V
V
SENSE_
= V
EE
V
EE_UVLO
V
EE_UVLOH
V
EE_OV
V
EE_OVH
V
EE_UV
V
DD
V
DD_UVLO
T
SHD
T
SHDH
V
AGND
- V
EE
, V
AGND
- V
EE
increasing
Ports shut down if: V
AGND
- V
EE
<
V
EE_UVLO
- V
EE_UVLOH
Ports shut down if: V
AGND
- V
EE
> V
EE_OV
,
V
AGND
- V
EE
increasing
V
EE_UV
event bit sets if: V
AGND
- V
EE
<
V
EE_UV
, V
AGND
- V
EE
increasing
I
DD
= 0 to 10mA
Port is shut down and device resets if the
junction temperature exceeds this limit,
temperature increasing (Note 4)
Temperature decreasing (Note 4)
V
OUT_
= V
AGND
, during idle
V
AGND
- V
EE
= 48V, V
OUT_
= V
EE
, during
power-on mode
Detection and classification off, port
shut down
V
OUT_
- V
EE
, OUT_ decreasing
3.0
40
3.3
2
+140
20
I
BOUT
R
DIS
PG
TH
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Maxim Integrated
│
3
MAX5980A
Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
Electrical Characteristics (continued)
(V
AGND
= 32V to 60V, V
EE
= V
DGND
= 0V, T
A
= -40°C to +105°C. All voltages are referenced to V
EE
, unless otherwise noted. Typical
values are at V
AGND
= 54V, T
A
= +25°C, and default register settings. Currents are positive when entering the pin, and negative
otherwise.) (Note 2)
PARAMETER
PGOOD Hysteresis
PGOOD Low-to-High Glitch Filter
LOAD DISCONNECT
DC Load Disconnect Threshold
Load Disconnect Time
DETECTION
Detection Probe Voltage (First
Phase)
Detection Probe Voltage (Second
Phase)
Current-Limit Protection
Short-Circuit Threshold
Open-Circuit Threshold
Resistor Detection Window
Resistor Rejection Window
CLASSIFICATION
Classification Probe Voltage
Current-Limit Protection
Classification Event Timing
Mark Event Voltage
Mark Event Current Limit
Mark Event Timing
V
CL
I
CL_LIM
t
CL_E
V
MARK
I
MARK_LIM
t
MARK_E
Class 0, Class 1
Class 1, Class 2
Classification current
Class 2, Class 3
thresholds between
Class 3, Class 4
classes
Class 4 upper limit
(Note 6)
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SYMBOL
PG
HYS
t
PGOOD
CONDITIONS
Time V
OUT_
- V
EE
has to exceed PGTH to
set the PGOOD_ bit in register 10h
Minimum V
SENSE_
allowed before
disconnect (DC disconnect active),
V
OUT_
= 0V
Time from V
SENSE_
< V
DCTH
to gate
shutdown (Note 5)
V
AGND
- V
DET
during the first detection
phase
V
AGND
- V
DET
during the second detection
phase
V
OUT_
= V
AGND
, current measured through
OUT_ during detection
If V
AGND
- V
OUT_
< V
DCP
after the first
detection phase, a short circuit to AGND is
detected
First point measurement current threshold
for open condition
(Note 5)
Detection rejects lower values
Detection rejects higher values
V
AGND
- V
OUT_
during classification
V
OUT_
= V
AGND
, current measured
through OUT_
V
AGND
- V
DET
during mark event
V
DET
= V
AGND
, during mark event
measure current through DET
MIN
TYP
220
MAX
UNITS
mV
2
4
ms
V
DCTH
t
DISC
1.25
300
1.875
2.5
400
mV
ms
V
DPH1
V
DPH2
I
DLIM
V
DCP
I
D_OPEN
R
DOK
R
DBAD
3.8
8.8
1.50
4
9.1
4.2
9.4
2
V
V
mA
V
µA
1.5
12.5
19
32
15.5
65
14
8
34
7
5.5
13.0
21
31
45
40
9
6.5
14.5
23
33
48
75
18
20
86
22
9.6
46
11
7.5
16.0
25
35
51
26.5
15.2
kΩ
kΩ
V
mA
ms
V
mA
ms
Classification Current Thresholds
I
CL
mA
Maxim Integrated
│
4
MAX5980A
Quad, IEEE 802.3at/af PSE Controller
for Power-over-Ethernet
Electrical Characteristics (continued)
(V
AGND
= 32V to 60V, V
EE
= V
DGND
= 0V, T
A
= -40°C to +105°C. All voltages are referenced to V
EE
, unless otherwise noted. Typical
values are at V
AGND
= 54V, T
A
= +25°C, and default register settings. Currents are positive when entering the pin, and negative
