FUJITSU SEMICONDUCTOR
DATA SHEET
DS501-00044-2v0-E
Memory FRAM
64 K (8 K
×
8) Bit I
2
C
MB85RC64TA
■
DESCRIPTION
The MB85RC64TA is an FRAM (Ferroelectric Random Access Memory) chip in a configuration of 8,192
words
×
8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the
nonvolatile memory cells.
Unlike SRAM, the MB85RC64TA is able to retain data without using a data backup battery.
The read/write endurance of the nonvolatile memory cells used for the MB85RC64TA has improved to be
at least 10
13
cycles, significantly outperforming Flash memory and E
2
PROM in the number.
The MB85RC64TA does not need a polling sequence after writing to the memory such as the case of Flash
memory or E
2
PROM.
■
FEATURES
• Bit configuration
• Two-wire serial interface
• Operating frequency
•
•
•
•
: 8,192 words
×
8 bits
: Fully controllable by two ports: serial clock (SCL) and serial data (SDA).
: 3.4 MHz (Max @HIGH SPEED MODE)
1 MHz (Max @FAST MODE PLUS)
Read/write endurance
: 10
13
times / byte
Data retention
: 10 years (
+
85
°C),
95 years (
+
55
°C),
over 200 years (
+
35
°C)
Operating power supply voltage : 1.8 V to 3.6 V
Low power consumption
: Operating power supply current 170
μA
(Typ @3.4 MHz)
Standby current 8
μA
(Typ)
Sleep current 4
μA
(Typ)
Operation ambient temperature range :
−
40
°C
to + 85
°C
Package
: 8-pin plastic SOP (FPT-8P-M09)
8-pin plastic SON (LCC-8P-M04)
RoHS compliant
•
•
Copyright 2016 FUJITSU SEMICONDUCTOR LIMITED
2016.10
MB85RC64TA
■
PIN ASSIGNMENT
(TOP VIEW)
(TOP VIEW)
A0
1
8
VDD
A0
1
2
3
4
8
7
6
5
VDD
WP
SCL
SDA
A1
2
7
WP
A1
A2
VSS
A2
3
6
SCL
VSS
4
5
SDA
(FPT-8P-M09)
(LCC-8P-M04)
■
PIN FUNCTIONAL DESCRIPTIONS
Pin
Number
Pin Name
Functional Description
Device Address pins
The MB85RC64TA can be connected to the same data bus up to 8 devices.
Device addresses are used in order to identify each of these devices. Connect
these pins to VDD pin or VSS pin externally. Only if the combination of VDD and
VSS pins matches a Device Address Code inputted from the SDA pin, the
device operates. In the open pin state, A0, A1 and A2 pins are internally pulled-
down and recognized as the “L” level.
Ground pin
Serial Data I/O pin
This is an I/O pin which performs bidirectional communication for both memory
address and writing/reading data. It is possible to connect multiple devices. It is
an open drain output, so a pull-up resistor is required to be connected to the ex-
ternal circuit.
Serial Clock pin
This is a clock input pin for input/output serial data. Data is sampled on the ris-
ing edge of the clock and output on the falling edge.
Write Protect pin
When the Write Protect pin is the “H” level, the writing operation is disabled.
When the Write Protect pin is the “L” level, the entire memory region can be
overwritten. The reading operation is always enabled regardless of the Write
Protect pin input level. The Write Protect pin is internally pulled down to VSS
pin, and that is recognized as the “L” level (write enabled) when the pin is the
open state.
Supply Voltage pin
1 to 3
A0 to A2
4
VSS
5
SDA
6
SCL
7
WP
8
VDD
2
DS501-00044-2v0-E
MB85RC64TA
■
BLOCK DIAGRAM
Serial/Parallel Converter
SDA
Row Decoder
WP
Control Logic
SCL
Address Counter
FRAM Array
8,192
×
8
Column Decoder/Sense Amp/
Write Amp
A0, A1, A2
■
I
2
C (Inter-Integrated Circuit)
The MB85RC64TA has the two-wire serial interface; the I
2
C bus, and operates as a slave device.
The I
2
C bus defines communication roles of “master” and “slave” devices, with the master side holding the
authority to initiate control. Furthermore, an I
2
C bus connection is possible where a single master device is
connected to multiple slave devices in a party-line configuration. In this case, it is necessary to assign a
unique device address to the slave device, the master side starts communication after specifying the slave
to communicate by addresses.
•
I
2
C Interface System Configuration Example
VDD
Pull-up
Resistors
SCL
SDA
I
2
C Bus
Master
I
2
C Bus
MB85RC64TA
A2
0
A1
0
A0
0
I
2
C Bus
MB85RC64TA
A2
0
A1
0
A0
1
I
2
C Bus
MB85RC64TA
A2
0
A1
1
A0
0
...
Device address
DS501-00044-2v0-E
3
MB85RC64TA
■
I
2
C COMMUNICATION PROTOCOL
The I
2
C bus is a two wire serial interface that uses a bidirectional data bus (SDA) and serial clock (SCL). A
data transfer can only be initiated by the master, which will also provide the serial clock for synchronization.
The SDA signal should change while the SCL is the “L” level. However, as an exception, when starting and
stopping communication sequence, the SDA is allowed to change while the SCL is the “H” level.
• Start Condition
To start read or write operations by the I
2
C bus, change the SDA input from the “H” level to the “L” level while
the SCL input is in the “H” level.
• Stop Condition
To stop the I
2
C bus communication, change the SDA input from the “L” level to the “H” level while the SCL
input is in the “H” level. In the reading operation, inputting the stop condition finishes reading and enters the
standby state. In the writing operation, inputting the stop condition finishes inputting the rewrite data and
enters the standby state.
•
Start Condition, Stop Condition
SCL
SDA
“H” or “L”
Start
Stop
Note : At the write operation, the FRAM device does not need the programming wait time (t
WC
) after issuing the
Stop Condition.
4
DS501-00044-2v0-E
MB85RC64TA
■
ACKNOWLEDGE (ACK)
In the I
2
C bus, serial data including address or memory information is sent in units of 8 bits. The acknowledge
signal indicates that every 8 bits of the data is successfully sent and received. The receiver side usually
outputs the “L” level every time on the 9th SCL clock after each 8 bits are successfully transmitted and
received. On the transmitter side, the bus is temporarily released to Hi-Z every time on this 9th clock to allow
the acknowledge signal to be received and checked. During this Hi-Z-released period, the receiver side pulls
the SDA line down to indicate the “L” level that the previous 8 bits communication is successfully received.
In case the slave side receives Stop condition before sending or receiving the ACK “L” level, the slave side
stops the operation and enters to the standby state. On the other hand, the slave side releases the bus state
after sending or receiving the NACK “H” level. The master side generates Stop condition or Start condition
in this released bus state.
•
Acknowledge timing overview diagram
SCL
1
2
3
8
9
SDA
The transmitter side should always release SDA on the
9th bit. At this time, the receiver side outputs a pull-down if
the previous 8 bits data are received correctly (ACK re-
sponse).
ACK
Start
DS501-00044-2v0-E
5
