MB96380 Series
F
2
MC-16FX 16-bit Proprietary
Microcontroller
MB96380 series is based on Cypress advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance).
The CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the
new 16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even
at the same operation frequency, reduced power consumption and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to
56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 17.8ns going
together with excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency
spectrum. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock
tree allows to select suitable operation frequencies for peripheral resources independent of the CPU speed.
Note: MB96384/385/F385/F388/F389 devices are under development and specification is preliminary. These products under
development may change its specification without notice.
Features
Technology
■
On-chip voltage regulator
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0.18m CMOS
CPU
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■
■
Internal voltage regulator supports reduced internal MCU
voltage, offering low EMI and low power consumption figures
F
2
MC-16FX CPU
Up to 56 MHz internal, 17.8 ns instruction cycle time
Optimized instruction set for controller applications (bit, byte,
word and long-word data types; 23 different addressing
modes; barrel shift; variety of pointers)
8-byte instruction execution queue
Signed multiply (16-bit
16-bit) and divide (32-bit/16-bit)
instructions available
Low voltage reset
■
Reset is generated when supply voltage is below minimum.
Code Security
■
Protects ROM content from unintended read-out
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■
Memory Patch Function
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■
Replaces ROM content
Can also be used to implement embedded debug support
System clock
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DMA
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On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)
3 MHz - 16 MHz external crystal oscillator clock (maximum
frequency when using ceramic resonator depends on
Q-factor).
Up to 56 MHz external clock for devices with fast clock input
feature
32-100 kHz subsystem quartz clock
100kHz/2MHz internal RC clock for quick and safe startup,
oscillator stop detection, watchdog
Clock source selectable from main- and subclock oscillator
(part number suffix “W”) and on-chip RC oscillator,
independently for CPU and 2 clock domains of peripherals.
Low Power Consumption - 13 operating modes : (different
Run, Sleep, Timer modes, Stop mode)
Clock modulator
Automatic transfer function independent of CPU, can be
assigned freely to resources
Interrupts
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Fast Interrupt processing
8 programmable priority levels
Non-Maskable Interrupt (NMI)
Timers
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Three independent clock timers (23-bit RC clock timer, 23-bit
Main clock timer, 17-bit Sub clock timer)
Watchdog Timer
■
■
Cypress Semiconductor Corporation
Document Number: 002-04582 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 28, 2016
MB96380 Series
CAN
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Input Capture Units
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Supports CAN protocol version 2.0 part A and B
ISO16845 certified
Bit rates up to 1 Mbit/s
32 message objects
Each message object has its own identifier mask
Programmable FIFO mode (concatenation of message
objects)
Maskable interrupt
Disabled Automatic Retransmission mode for Time Triggered
CAN applications
Programmable loop-back mode for self-test operation
16-bit wide
Signals an interrupt upon external event
Rising edge, falling edge or rising & falling edge sensitive
Output Compare Units
■
■
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16-bit wide
Signals an interrupt when a match with 16-bit I/O Timer occurs
A pair of compare registers can be used to generate an output
signal.
Programmable Pulse Generator
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16-bit down counter, cycle and duty setting registers
Interrupt at trigger, counter borrow and/or duty match
PWM operation and one-shot operation
Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock
as counter clock and Reload timer overflow as clock input
Can be triggered by software or reload timer
USART
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Full duplex USARTs (SCI/LIN)
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different
synchronous serial protocols
LIN functionality working either as master or slave LIN device
Stepper Motor Controller
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I
2
C
■
■
Stepper Motor Controller with integrated high current output
drivers
Four high current outputs for each channel
Two synchronized 8/10-bit PWMs per channel
Internal prescaling for PWM clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10,
1/12, 1/16 of peripheral clock
Separate power supply for high current output drivers
Up to 400 kbps
Master and Slave functionality, 8-bit and 10-bit addressing
A/D converter
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SAR-type
10-bit resolution
Signals interrupt on conversion end, single conversion mode,
continuous conversion mode, stop conversion mode, activation
by software, external trigger or reload timer
LCD Controller
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LCD controller with up to 4 COM × 65 SEG
Internal or external voltage generation
Duty cycle: Selectable from options: 1/2, 1/3 and 1/4
Fixed 1/3 bias
Programmable frame period
Clock source selectable from three options (peripheral clock,
subclock or RC oscillator clock)
On-chip drivers for internal divider resistors or external divider
resistors
On-chip data memory for display
LCD display can be operated in Timer Mode
Blank display: selectable
All SEG, COM and V pins can be switched between general
and specialized purposes
External divided resistors can be also used to shut off the
current when LCD is deactivated
A/D Converter Reference Voltage switch
■
2 independent positive A/D converter reference voltages
available
Reload Timers
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■
16-bit wide
Prescaler with 1/2
1
, 1/2
2
, 1/2
3
, 1/2
4
, 1/2
5
, 1/2
6
of peripheral
clock frequency
Event count function
Free Running Timers
■
Signals an interrupt on overflow, supports timer clear upon
match with Output Compare (0, 4), Prescaler with 1, 1/2
1
, 1/2
2
,
1/2
3
, 1/2
4
, 1/2
5
, 1/2
6
, 1/2
7
,1/2
8
of peripheral clock frequency
Document Number: 002-04582 Rev. *A
Page 2 of 117
MB96380 Series
Sound Generator
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Alarm comparator
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8-bit PWM signal is mixed with tone frequency from 16-bit
reload counter
PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of peripheral
clock
Monitors an external voltage and generates an interrupt in case
of a voltage lower or higher than the defined thresholds
Threshold voltages defined externally or generated internally
Status is readable, interrupts can be masked separately
Real Time Clock
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I/O Ports
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Can be clocked either from sub oscillator (devices with part
number suffix “W”), main oscillator or from the RC oscillator
Facility to correct oscillation deviation of Sub clock or RC
oscillator clock (clock calibration)
Read/write accessible second/minute/hour registers
Can signal interrupts every half
second/second/minute/hour/day
Internal clock divider and prescaler provide exact 1s clock
Virtually all external pins can be used as general purpose I/O
All push-pull outputs (except when used as I2C SDA/SCL line)
Bit-wise programmable as input/output or peripheral signal
Bit-wise programmable input enable
Bit-wise programmable input levels: Automotive /
CMOS-Schmitt trigger / TTL
Bit-wise programmable pull-up resistor
Bit-wise programmable output driving strength for EMI
optimization
External Interrupts
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■
Edge sensitive or level sensitive
Interrupt mask and pending bit per channel
Each available CAN channel RX has an external interrupt for
wake-up
Selected USART channels SIN have an external interrupt for
wake-up
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Package
120-pin plastic LQFP
Flash Memory
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Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles: 10,000 times
Data retention time: 20 years
Erase can be performed on each sector individually
Sector protection
Flash Security feature to protect the content of the Flash
Low voltage detection during Flash erase
Non Maskable Interrupt
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Disabled after reset
Once enabled, can not be disabled other than by reset.
Level high or level low sensitive
Pin shared with external interrupt 0.
External bus interface
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8-bit or 16-bit bidirectional data
Up to 24-bit addresses
6 chip select signals
Multiplexed address/data lines
Non-multiplexed address/data lines
Wait state request
External bus master possible
Timing programmable
Document Number: 002-04582 Rev. *A
Page 3 of 117
MB96380 Series
Contents
Product Lineup ................................................................. 5
Block Diagram .................................................................. 7
Pin Assignment ................................................................ 8
Pin Function Description ................................................. 9
Pin Circuit Type .............................................................. 12
I/O Circuit Type ............................................................... 14
Memory Map .................................................................... 19
RAMSTART/END and External Bus End Addresses ... 20
User ROM Memory Map for Flash Devices .................. 21
User ROM Memory Map for Mask Rom Devices .......... 23
Serial Programming Communication Interface ........... 24
I/O Map ............................................................................. 25
Interrupt Vector Table .................................................... 55
Handling Devices ............................................................ 58
Latch-up prevention ................................................... 58
Unused pins handling ................................................ 58
External clock usage ................................................. 58
Unused sub clock signal ............................................ 59
Notes on PLL clock mode operation ......................... 59
Power supply pins (VCC/VSS) .................................. 59
Crystal oscillator and ceramic resonator circuit ......... 59
Turn on sequence of power supply to
A/D converter and analog inputs ............................... 59
Pin handling when not using the A/D converter ........ 59
Notes on Power-on .................................................... 59
Stabilization of power supply voltage ........................ 59
SMC power supply pins ............................................. 60
Serial communication ................................................ 60
Electrical Characteristics ............................................... 61
Absolute Maximum Ratings ....................................... 61
Recommended Operating Conditions ....................... 64
DC characteristics ..................................................... 65
AC Characteristics ..................................................... 77
Analog Digital Converter ........................................... 99
Alarm Comparator ................................................... 103
Low Voltage Detector characteristics ...................... 105
FLASH memory program/erase characteristics ...... 107
Example Characteristics .............................................. 108
Package Dimension MB96(F)38x LQFP 120P ............ 112
Ordering Information .................................................... 113
Revision History ........................................................... 114
Document History ......................................................... 116
Document Number: 002-04582 Rev. *A
Page 4 of 117
MB96380 Series
1. Product Lineup
Features
Product type
Product options
YS
RS
YW
RW
TS
HS
TW
HW
Flash/ROM
128KB
160KB
288KB
416KB
576KB
[Flash A: 544KB,
Flash B: 32KB]
832KB
[Flash A: 544KB,
Flash B: 288KB]
Package
DMA
USART
I2C
A/D Converter
A/D Converter Reference
Voltage switch
16-bit Reload Timer
16-bit Free-Running Timer
16-bit Output Compare
RAM
6KB
8KB
16KB
16KB
28KB
ROM/Flash memory
emulation by
external RAM,
92KB internal RAM
MB96384Y
*1
, MB96384R
*1
MB96385Y
*1
, MB96385R
*1
, MB96F385Y
*1
, MB96F385R
*1
MB96F386Y, MB96F386R
MB96F387Y, MB96F387R
MB96F388T
*1
, MB96F388H
*1
NA
Low voltage reset persistently on / Single clock
Low voltage reset can be disabled / Single clock
Low voltage reset persistently on / Dual clock
Low voltage reset can be disabled / Dual clock
indep. 32KB Flash / Low voltage reset persistently on / Single clock
indep. 32KB Flash / Low voltage reset can be disabled / Single clock
indep. 32KB Flash / Low voltage reset persistently on / Dual clock
indep. 32KB Flash / Low voltage reset can be disabled / Dual clock
MB96V300B
Evaluation sample
MB96(F)38x
Flash product: MB96F38x
Mask ROM product: MB9638x
32KB
BGA416
16 channels
10 channels
2 channels
40 channels
yes
6 channels + 1
channel (for PPG)
4 channels
12 channels
MB96F389Y
*1
, MB96F389R
*1
,
FPT-120P-M21
7 channels
5 channels
1 channel
16 channels
Only for MB96F386Y, MB96F386R, MB96F387Y, MB96F387R
4 channels + 1 channel (for PPG)
2 channels
4 channels
Document Number: 002-04582 Rev. *A
Page 5 of 117
