FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20869-3E
FLASH MEMORY
CMOS
32M (4M
×
8) BIT
MBM29F033C
-70/-90/-12
s
FEATURES
• Single 5.0 V read, write, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Pinout and software compatible with single-power supply Flash
Superior inadvertent write protection
• 40-pin TSOP (I) (Package suffix: PTN-Normal Bend Type, PTR-Reversed Bend Type)
• Minimum 100,000 write/erase cycles
• High performance
70 ns maximum access time
• Sector erase architecture
Uniform sectors of 64K bytes each
Any combination of sectors can be erased. Also supports full chip erase
• Embedded Erase
TM
Algorithms
Automatically preprograms and erases the chip or any sector
• Embedded Program
TM
Algorithms
Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/BUSY output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Low V
CC
write inhibit
≤
3.2 V
• Hardware RESET pin
Resets internal state machine to the read mode
• Erase Suspend/Resume
Supports reading or programming data to a sector not being erased
• Sector group protection
Hardware method that disables any combination of sector groups from write or erase operation (a sector group
consists of 4 adjacent sectors of 64K bytes each)
• Temporary sector groups unprotection
Hardware method temporarily enable any combination of sectors from write or erase operations
Embedded Erase™, Embedded Program™ and ExpressFlash™ are trademarks of Advanced Micro Devices, Inc.
MBM29F033C
-70/-90/-12
s
PACKAGE
40-pin plastic TSOP (I)
Marking Side
40-pin plastic TSOP (I)
Marking Side
(FPT-40P-M06)
(FPT-40P-M07)
2
MBM29F033C
-70/-90/-12
s
GENERAL DESCRIPTION
The MBM29F033C is a 32M-bit, 5.0 V-Only Flash memory organized as 4M bytes of 8 bits each. The 2M bytes
of data is divided into 64 sectors of 64K bytes for flexible erase capability. The 8 bit of data will appear on DQ
0
to DQ
7
. The MBM29F033C is offered in a 40-pin TSOP package. This device is designed to be programmed in-
system with the standard system 5.0 V V
CC
supply. A 12.0 V V
PP
is not required for program or erase operations.
The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29F033C offers access times between 70 ns and 120 ns allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29F033C is command set compatible with JEDEC standard single-supply Flash standard. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the device is
similar to reading from 12.0 V Flash or EPROM devices.
The MBM29F033C is programmed by executing the program command sequence. This will invoke the Embedded
Program
TM
Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. Each sector can be programmed and verified in less than 0.5 seconds. Erase is accomplished
by executing the erase command sequence. This will invoke the Embedded Erase
TM
Algorithm which is an
internal algorithm that automatically preprograms the array if it is not already programmed before executing the
erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell
margin.
This device also features a sector erase architecture. The sector erase mode allows for sectors of memory to
be erased and reprogrammed without affecting other sectors. A sector is typically erased and verified within one
second (if already completely preprogrammed). The MBM29F033C is erased when shipped from the factory.
The MBM29F033C device also features hardware sector group protection. This feature will disable both program
and erase operations in any combination of eight sector groups of memory.
A sector group consists of four
adjacent sectors grouped in the following pattern: sectors 0-3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, 28-31, 32-
35, 36-39, 40-43, 44-47, 48-51, 52-55, 56-59, and 60-63.
Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of
time to read data from or program data to a non-busy sector. Thus, true background erase can be achieved.
The device features single 5.0 V power supply operation for both read and program functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations during power transitions. The end of program or erase is detected by Data Polling of
DQ
7
, or by the Toggle Bit I feature on DQ
6
or RY/BY output pin. Once the end of a program or erase cycle has
been completed, the device automatically resets to the read mode.
The MBM29F033C also has a hardware RESET pin. When this pin is driven low, execution of any Embedded
Program or Embedded Erase operations will be terminated. The internal state machine will then be reset into
the read mode. The RESET pin may be tied to the system reset circuity. Therefore, if a system reset occurs
during the Embedded Program or Embedded Erase operation, the device will be automatically reset to a read
mode. This will enable the system microprocessor to read the boot-up firmware from the Flash memory.
Fujitsu's Flash technology combines years of EPROM and E
2
PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29F033C memory electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM
programming mechanism of hot electron injection.
3
MBM29F033C
-70/-90/-12
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE
• Sixty four 64K byte sectors
• 16 sector groups each of which consists of 4 adjacent sectors in the following pattern; sectors 0-3, 4-7, 8-11,
12-15, 16-19, 20-23, 24-27, 28-31, 32-35, 36-39, 40-43, 44-47, 48-51, 52-55, 56-59, and 60-63.
• Individual-sector or multiple-sector erase capability
• Sector group protection is user-definable
SA31
SA30
SA29
SA28
64K byte
64K byte
64K byte
64K byte
1FFFFFH
1EFFFFH
1DFFFFH
1CFFFFH
1BFFFFH
1AFFFFH
19FFFFH
18FFFFH
17FFFFH
16FFFFH
15FFFFH
14FFFFH
13FFFFH
12FFFFH
11FFFFH
10FFFFH
32 Sectors Total
0FFFFFH
0EFFFFH
0DFFFFH
0CFFFFH
0BFFFFH
0AFFFFH
09FFFFH
08FFFFH
07FFFFH
06FFFFH
05FFFFH
04FFFFH
SA3
SA2
SA1
SA0
4
64K byte
64K byte
64K byte
64K byte
03FFFFH
02FFFFH
01FFFFH
00FFFFH
000000H
SA35
Sector
Group 0 SA33
SA32
SA34
64K byte
64K byte
64K byte
64K byte
32 Sectors Total
SA63
SA62
Sector
Group 7
SA61
SA60
64K byte
64K byte
64K byte
64K byte
3FFFFFH
3EFFFFH
3DFFFFH
3CFFFFH
3BFFFFH
3AFFFFH
39FFFFH
38FFFFH
37FFFFH
36FFFFH
35FFFFH
34FFFFH
33FFFFH
32FFFFH
31FFFFH
30FFFFH
2FFFFFH
2EFFFFH
2DFFFFH
2CFFFFH
2BFFFFH
2AFFFFH
29FFFFH
28FFFFH
27FFFFH
26FFFFH
25FFFFH
24FFFFH
23FFFFH
22FFFFH
21FFFFH
20FFFFH
200000H
Sector
Group 8
Sector
Group 15
MBM29F033C
-70/-90/-12
s
PRODUCT LINE UP
Part No.
Ordering Part No.
Max. Address Access Time ( ns )
Max. CE Access Time (ns)
Max. OE Access Time (ns)
V
CC
= 5.0 V
±
5
%
V
CC
= 5.0 V
±
10
%
-70
—
70
70
40
MBM29F033C
—
-90
90
90
40
—
-12
120
120
50
s
BLOCK DIAGRAM
RY/BY
Buffer
V
CC
V
SS
DQ
0
to DQ
7
RY/BY
Erase Voltage
Generator
Input/Output
Buffers
WE
State
Control
RESET
Command
Register
Program Voltage
Generator
CE
OE
Chip Enable
Output Enable
Logic
STB
Data Latch
STB
Y-Decoder
Y-Gating
Low V
CC
Detector
Timer for
Program/Erase
Address
Latch
X-Decoder
Cell Matrix
A
0
to A
21
5
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