MBM29LV200TC-12PFTR,MBM29LV200TC-12PFTR pdf中文资料,MBM29LV200TC-12PFTR引脚图,MBM29LV200TC-12PFTR电路-Datasheet-电子工程世界

器件参数

参数名称

属性值

是否Rohs认证

不符合

厂商名称

SPANSION

零件包装代码

TSOP1

包装说明

PLASTIC, REVERSE, TSOP1-48

针数

Reach Compliance Code

not_compliant

ECCN代码

EAR99

最长访问时间

120 ns

其他特性

CONFIGURABLE AS 128K X 16; 100000 PROGRAM/ERASE CYCLES MIN

备用内存宽度

启动块

TOP

命令用户界面

YES

数据轮询

YES

耐久性

100000 Write/Erase Cycles

JESD-30 代码

R-PDSO-G48

JESD-609代码

长度

18.4 mm

内存密度

2097152 bit

内存集成电路类型

FLASH

内存宽度

湿度敏感等级

功能数量

部门数/规模

1,2,1,3

端子数量

字数

262144 words

字数代码

256000

工作模式

ASYNCHRONOUS

最高工作温度

85 °C

最低工作温度

-40 °C

组织

256KX8

封装主体材料

PLASTIC/EPOXY

封装代码

TSOP1-R

封装等效代码

TSSOP48,.8,20

封装形状

RECTANGULAR

封装形式

SMALL OUTLINE, THIN PROFILE

并行/串行

PARALLEL

峰值回流温度（摄氏度）

240

电源

3/3.3 V

编程电压

3 V

认证状态

Not Qualified

就绪/忙碌

YES

反向引出线

YES

座面最大高度

1.2 mm

部门规模

16K,8K,32K,64K

最大待机电流

0.000005 A

最大压摆率

0.035 mA

最大供电电压 (Vsup)

3.6 V

最小供电电压 (Vsup)

2.7 V

标称供电电压 (Vsup)

3 V

表面贴装

YES

技术

CMOS

温度等级

INDUSTRIAL

端子面层

Tin/Lead (Sn/Pb)

端子形式

GULL WING

端子节距

0.5 mm

端子位置

DUAL

处于峰值回流温度下的最长时间

切换位

YES

类型

NOR TYPE

宽度

12 mm

Base Number Matches

文档预览

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20865-3E

FLASH MEMORY

CMOS

2M (256K

8/128K

16) BIT

MBM29LV200TC

-70/-90/-12

/MBM29LV200BC

-70/-90/-12

FEATURES

• Single 3.0 V read, program, and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Uses same software commands as E

PROMs

• Compatible with JEDEC-standard world-wide pinouts

48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)

44-pin SOP (Package suffix: PF)

• Minimum 100,000 program/erase cycles

• High performance

70 ns maximum access time

• Sector erase architecture

One 8K word, two 4K words, one 16K word, and three 32K words sectors in word mode

One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes sectors in byte mode

Any combination of sectors can be concurrently erased. Also supports full chip erase

• Boot Code Sector Architecture

T = Top sector

B = Bottom sector

• Embedded Erase

Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program

Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode

• Low V

write inhibit

≤

2.5 V

• Erase Suspend/Resume

Suspends the erase operation to allow a read in another sector within the same device

(Continued)

Embedded Erase

and Embedded Program

are trademarks of Advanced Micro Devices, Inc.

MBM29LV200TC

-70/-90/-12

/MBM29LV200BC

-70/-90/-12

(Continued)

• Sector protection

Hardware method disables any combination of sectors from program or erase operations

• Sector Protection set function by Extended sector Protect command

• Temporary sector unprotection

Temporary sector unprotection via the RESET pin

PACKAGE

48-pin plastic TSOP(I)

48-pin plasticTSOP(I)

44-pin plastic SOP

Marking Side

(FPT-48P-M19)

(FPT-48P-M20)

(FPT-44P-M16)

MBM29LV200TC

-70/-90/-12

/MBM29LV200BC

-70/-90/-12

GENERAL DESCRIPTION

The MBM29LV200TC/BC are a 8M-bit, 3.0 V-only Flash memory organized as 256K bytes of 8 bits each or 128K

words of 16 bits each. The MBM29LV200TC/BC are offered in 48-pin TSOP(I) and 44-pin SOP packages. These

devices are designed to be programmed in-system with the standard system 3.0 V V

supply. 12.0 V V

and

5.0 V V

are not required for write or erase operations. The devices can also be reprogrammed in standard

EPROM programmers.

The standard MBM29LV200TC/BC offer access times 70 ns and 120 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),

write enable (WE), and output enable (OE) controls.

The MBM29LV200TC/BC are pin and command set compatible with JEDEC standard E

PROMs. Commands

are written to the command register using standard microprocessor write timings. Register contents serve as

input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and erase operations. Reading data out of the devices

is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29LV200TC/BC are programmed by executing the program command sequence. This will invoke the

Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths

and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.

Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase

Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed

before executing the erase operation. During erase, the devices automatically time the erase pulse widths and

verify proper cell margin.

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)

The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29LV200TC/BC are erased when shipped from the

factory.

The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V

detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ

by the Toggle Bit feature on DQ

, or the RY/BY output pin. Once the end of a program or erase cycle has been

completed, the devices internally reset to the read mode.

Fujitsu’s Flash technology combines years of EPROM and E

PROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The MBM29LV200TC/BC memories electrically erase the entire chip

or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one

byte/word at a time using the EPROM programming mechanism of hot electron injection.

MBM29LV200TC

-70/-90/-12

/MBM29LV200BC

-70/-90/-12

FLEXIBLE SECTOR-ERASE ARCHITECTURE

• One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes

• Individual-sector, multiple-sector, or bulk-erase capability

• Individual or multiple-sector protection is user definable.

(×8)

16K byte

(×16)

64K byte

(×8)

(×16)

3FFFFH 1FFFFH

3BFFFH 1DFFFH

8K byte

39FFFH 1CFFFH

8K byte

37FFFH 1BFFFH

32K byte

2FFFFH 17FFFH

64K byte

1FFFFH 0FFFFH

64K byte

0FFFFH 07FFFH

64K byte

00000H 00000H

MBM29LV200TC Sector Architecture

16K byte

8K byte

32K byte

64K byte

3FFFFH 1FFFFH

2FFFFH 17FFFH

1FFFFH 0FFFFH

0FFFFH 07FFFH

07FFFH 03FFFH

05FFFH 02FFFH

03FFFH 01FFFH

00000H

MBM29LV200BC Sector Architecture

MBM29LV200TC

-70/-90/-12

/MBM29LV200BC

-70/-90/-12

PRODUCT LINE UP

Part No.

= 3.3 V

Ordering Part No.

= 3.0 V

Max. Address Access Time (ns)

Max. CE Access Time (ns)

Max. OE Access Time (ns)

+0.3 V

–0.3 V

+0.6 V

–0.3 V

MBM29LV200TC/MBM29LV200BC

-70

—

-90

—

-12

120

BLOCK DIAGRAM

RY/BY

Buffer

to DQ

RY/BY

Erase Voltage

Generator

Input/Output

Buffers

BYTE

RESET

State

Control

Command

Program Voltage

Generator

Chip Enable

Output Enable

Logic

STB

Data Latch

STB

Y-Decoder

Y-Gating

Low V

Detector

Timer for

Program/Erase

Address

Latch

X-Decoder

Cell Matrix

to A

-1

参数对比

与MBM29LV200TC-12PFTR相近的元器件有：MBM29LV200BC-12PFTN、MBM29LV200BC-12PFTN-E1、MBM29LV200BC-12PFTR、550222T450CF2B、MBM29LV200TC-12PFTN、MBM29LV200TC-12PFTN-E1、MBM29LV200TC-12PFTR-E1。描述及对比如下：

型号	MBM29LV200TC-12PFTR	MBM29LV200BC-12PFTN	MBM29LV200BC-12PFTN-E1	MBM29LV200BC-12PFTR	550222T450CF2B	MBM29LV200TC-12PFTN	MBM29LV200TC-12PFTN-E1	MBM29LV200TC-12PFTR-E1
描述	Flash, 256KX8, 120ns, PDSO48, PLASTIC, REVERSE, TSOP1-48	Flash, 256KX8, 120ns, PDSO48, PLASTIC, TSOP1-48	Flash, 256KX8, 120ns, PDSO48, PLASTIC, TSOP1-48	Flash, 256KX8, 120ns, PDSO48, PLASTIC, REVERSE, TSOP1-48	High Ripple, Long Life, Computer Grade	Flash, 256KX8, 120ns, PDSO48, PLASTIC, TSOP1-48	Flash, 256KX8, 120ns, PDSO48, PLASTIC, TSOP1-48	Flash, 256KX8, 120ns, PDSO48, PLASTIC, REVERSE, TSOP1-48
是否Rohs认证	不符合	不符合	-	不符合	-	不符合	-	符合
厂商名称	SPANSION	SPANSION	SPANSION	SPANSION	-	SPANSION	SPANSION	SPANSION
零件包装代码	TSOP1	TSOP1	TSOP1	TSOP1	-	TSOP1	TSOP1	TSOP1
包装说明	PLASTIC, REVERSE, TSOP1-48	PLASTIC, TSOP1-48	PLASTIC, TSOP1-48	PLASTIC, REVERSE, TSOP1-48	-	PLASTIC, TSOP1-48	PLASTIC, TSOP1-48	PLASTIC, REVERSE, TSOP1-48
针数	48	48	48	48	-	48	48	48
Reach Compliance Code	not_compliant	not_compliant	unknown	not_compliant	-	not_compliant	unknown	compliant
ECCN代码	EAR99	EAR99	EAR99	EAR99	-	EAR99	EAR99	EAR99
最长访问时间	120 ns	120 ns	120 ns	120 ns	-	120 ns	120 ns	120 ns
其他特性	CONFIGURABLE AS 128K X 16; 100000 PROGRAM/ERASE CYCLES MIN	CONFIGURABLE AS 128K X 16; 100000 PROGRAM/ERASE CYCLES MIN	CONFIGURABLE AS 128K X 16; 100000 PROGRAM/ERASE CYCLES MIN	CONFIGURABLE AS 128K X 16; 100000 PROGRAM/ERASE CYCLES MIN	-	CONFIGURABLE AS 128K X 16; 100000 PROGRAM/ERASE CYCLES MIN	CONFIGURABLE AS 128K X 16; 100000 PROGRAM/ERASE CYCLES MIN	CONFIGURABLE AS 128K X 16; 100000 PROGRAM/ERASE CYCLES MIN
启动块	TOP	BOTTOM	BOTTOM	BOTTOM	-	TOP	TOP	TOP
JESD-30 代码	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	-	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48
JESD-609代码	e0	e0	-	e0	-	e0	-	e3
长度	18.4 mm	18.4 mm	18.4 mm	18.4 mm	-	18.4 mm	18.4 mm	18.4 mm
内存密度	2097152 bit	2097152 bit	2097152 bit	2097152 bit	-	2097152 bit	2097152 bit	2097152 bit
内存集成电路类型	FLASH	FLASH	FLASH	FLASH	-	FLASH	FLASH	FLASH
内存宽度	8	8	8	8	-	8	8	8
湿度敏感等级	3	3	3	3	-	3	3	-
功能数量	1	1	1	1	-	1	1	1
端子数量	48	48	48	48	-	48	48	48
字数	262144 words	262144 words	262144 words	262144 words	-	262144 words	262144 words	262144 words
字数代码	256000	256000	256000	256000	-	256000	256000	256000
工作模式	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	-	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
最高工作温度	85 °C	85 °C	85 °C	85 °C	-	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-	-40 °C	-40 °C	-40 °C
组织	256KX8	256KX8	256KX8	256KX8	-	256KX8	256KX8	256KX8
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSOP1-R	TSOP1	TSOP1	TSOP1-R	-	TSOP1	TSOP1	TSOP1-R
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	-	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	-	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	240	240	240	240	-	240	240	260
编程电压	3 V	3 V	3 V	3 V	-	3 V	3 V	3 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.2 mm	1.2 mm	1.2 mm	1.2 mm	-	1.2 mm	1.2 mm	1.2 mm
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	-	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	-	2.7 V	2.7 V	2.7 V
标称供电电压 (Vsup)	3 V	3 V	3 V	3 V	-	3 V	3 V	3 V
表面贴装	YES	YES	YES	YES	-	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	-	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	-	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	-	MATTE TIN
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	-	GULL WING	GULL WING	GULL WING
端子节距	0.5 mm	0.5 mm	0.5 mm	0.5 mm	-	0.5 mm	0.5 mm	0.5 mm
端子位置	DUAL	DUAL	DUAL	DUAL	-	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	30	30	30	30	-	30	30	40
类型	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	-	NOR TYPE	NOR TYPE	NOR TYPE
宽度	12 mm	12 mm	12 mm	12 mm	-	12 mm	12 mm	12 mm