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MC10EP195, MC100EP195
3.3V ECL Programmable
Delay Chip
The MC10/100EP195 is a Programmable Delay Chip (PDC)
designed primarily for clock deskewing and timing adjustment. It
provides variable delay of a differential NECL/PECL input transition.
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The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 3. The delay
increment of the EP195 has a digitally selectable resolution of about
MARKING
DIAGRAM*
10 ps and a net range of up to 10.2 ns. The required delay is selected by
the 10 data select inputs D[9:0] values and controlled by the LEN
(pin 10). A LOW level on LEN allows a transparent LOAD mode of
MCXXX
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
EP195
will LOCK and HOLD current values present against any subsequent
AWLYYWWG
LQFP−32
changes in D[10:0]. The approximate delay values for varying tap
FA SUFFIX
32
numbers correlating to D0 (LSB) through D9 (MSB) are shown in
CASE 873A
Table 6 and Figure 4.
1
Because the EP195 is designed using a chain of multiplexers it has a
fixed minimum delay of 2.2 ns. An additional pin D10 is provided for
controlling Pins 14 and 15, CASCADE and CASCADE, also latched
1
by LEN, in cascading multiple PDCs for increased programmable
MCXXX
range. The cascade logic allows full control of multiple PDCs.
1 32
EP195
Switching devices from all “1” states on D[0:9] with SETMAX LOW
AWLYYWWG
QFN32
to all “0” states on D[0:9] with SETMAX HIGH will increase the
G
MN SUFFIX
delay equivalent to “D0”, the minimum increment.
CASE 488AM
Select input pins D[10:0] may be threshold controlled by
combinations of interconnects between V
EF
(pin 7) and V
CF
(pin 8)
XXX
= 10 or 100
for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input
A
= Assembly Location
levels, leave V
CF
and V
EF
open. For ECL operation, short V
CF
and
WL, L = Wafer Lot
V
EF
(Pins 7 and 8). For LVTTL level operation, connect a 1.5 V
YY, Y
= Year
supply reference to V
CF
and leave open V
EF
pin. The 1.5 V reference
WW, W = Work Week
G or
G
= Pb−Free Package
voltage to V
CF
pin can be accomplished by placing a 2.2 kW resistor
(Note: Microdot may be in either location)
between V
CF
and V
EE
for a 3.3 V power supply.
*For additional marking information, refer to
The V
BB
pin, an internally generated voltage supply, is available to
Application Note AND8002/D.
this device only. For single−ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
ORDERING INFORMATION
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
See detailed ordering and shipping information in the package
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
dimensions section on page 17 of this data sheet.
to 0.5 mA. When not used, V
BB
should be left open.
The 100 Series contains temperature compensation.
•
Maximum Input Clock Frequency >1.2 GHz Typical
•
Open Input Default State
•
Programmable Range: 0 ns to 10 ns
•
Safety Clamp on Inputs
•
Delay Range: 2.2 ns to 12.2 ns
•
A Logic High on the EN Pin Will Force Q to Logic
Low
•
10 ps Increments
•
D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL
•
PECL Mode Operating Range:
Inputs
V
CC
= 3.0 V to 3.6 V with V
EE
= 0 V
•
V
BB
Output Reference Voltage
•
NECL Mode Operating Range:
•
Pb−Free Packages are Available
V
CC
= 0 V with V
EE
=
−3.0
V to
−3.6
V
©
Semiconductor Components Industries, LLC, 2009
April, 2009
−
Rev. 18
1
Publication Order Number:
MC10EP195/D
MC10EP195, MC100EP195
V
EE
D2
D1
D7
32
D8
D9
D10
IN
IN
V
BB
V
EF
V
CF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MC10EP195
MC100EP195
D8
D9
D10
IN
IN
V
BB
V
EF
V
CF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D6
31
32
D5
30
D4
29
D3
27
28
26
25
24
23
22
21
20
19
18
17
16
V
EE
D0
V
CC
Q
Q
V
CC
V
CC
NC
Figure 1. 32−Lead LQFP Pinout
(Top View)
V
EE
Figure 2. 32−Lead QFN
(Top View)
LEN
D7
V
EE
31
SETMIN
LEN
SETMAX
D5
30
V
CC
CASCADE
CASCADE
EN
V
EE
D6
D4
29
D3
27
D2
D1
28
26
25
24
23
22
21
20
19
18
17
V
EE
D0
V
CC
Q
Q
V
CC
V
CC
NC
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2
SETMIN
SETMAX
V
CC
CASCADE
CASCADE
EN
Exposed Pad (EP)
MC10EP195, MC100EP195
Table 1. PIN DESCRIPTION
Pin
23, 25, 26, 27,
29, 30, 31, 32,
1, 2
3
4
5
6
7
8
9, 24, 28
Name
D[0:9]
I/O
LVCMOS, LVTTL,
ECL Input
LVCMOS, LVTTL,
ECL Input
ECL Input
ECL Input
−
−
−
−
Default State
Low
Description
Single−Ended Parallel Data Inputs [0:9]. Internal 75 kW to V
EE
.
(Note 1)
Single−Ended CASCADE/CASCADE Control Input. Internal 75 kW
to V
EE
. (Note 1)
Noninverted Differential Input. Internal 75 kW to V
EE
.
Inverted Differential Input. Internal 75 kW to V
EE
and 36.5 kW to
V
CC
.
ECL Reference Voltage Output
Reference Voltage for ECL Mode Connection
LVCMOS, ECL, OR LVTTL Input Mode Select
Negative Supply Voltage. All V
EE
Pins must be Externally
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
Positive Supply Voltage. All V
CC
Pins must be externally
Connected to Power Supply to Guarantee Proper Operation.
(Note 2)
Single−ended D pins LOAD / HOLD input. Internal 75 kW to V
EE
.
Single−ended Minimum Delay Set Logic Input. Internal 75 kW to
V
EE
. (Note 1)
Single−ended Maximum Delay Set Logic Input. Internal 75 kW to
V
EE
. (Note 1)
Inverted Differential Cascade Output for D[10]. Typically Terminated
with 50
W
to V
TT
= V
CC
−
2 V.
Noninverted Differential Cascade Output. for D[10] Typically
Terminated with 50
W
to V
TT
= V
CC
−
2 V.
Single−ended Output Enable Pin. Internal 75 kW to V
EE
.
No Connect. The NC Pin is Electrically Connected to the Die and
”MUST BE” Left Open
Noninverted Differential Output. Typically Terminated with 50
W
to
V
TT
= V
CC
−
2 V.
Inverted Differential Output. Typically Terminated with 50
W
to
V
TT
= V
CC
−
2 V.
D[10]
IN
IN
V
BB
V
EF
V
CF
V
EE
Low
Low
High
−
−
−
−
13, 18, 19, 22
V
CC
−
−
10
11
12
14
15
16
17
21
20
LEN
SETMIN
SETMAX
CASCADE
CASCADE
EN
NC
Q
Q
ECL Input
ECL Input
ECL Input
ECL Output
ECL Output
ECL Input
−
ECL Output
ECL Output
Low
Low
Low
−
−
Low
−
−
−
1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs.
2. All V
CC
and V
EE
pins must be externally connected to Power Supply to guarantee proper operation.
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3
MC10EP195, MC100EP195
Table 2. CONTROL PIN
Pin
EN
State
LOW (Note 3)
Function
Input Signal is Propagated to the Output
HIGH
LEN
LOW (Note 3)
HIGH
SETMIN
LOW (Note 3)
HIGH
SETMAX
LOW (Note 3)
HIGH
D10
LOW (Note 3)
HIGH
Output Holds Logic Low State
Transparent or LOAD mode for real time delay values present on D[0:10].
LOCK and HOLD mode for delay values on D[0:10]; further changes on D[0:10]
are not recognized and do not affect delay.
Output Delay set by D[0:10]
Set Minimum Output Delay
Output Delay set by D[0:10]
Set Maximum Output Delay
CASCADE Output LOW, CASCADE Output HIGH
CASCADE Output LOW, CASCADE Output HIGH
3. Internal pulldown resistor will provide a logic LOW if pin is left unconnected.
Table 3. CONTROL D[0:10] INTERFACE
V
CF
V
CF
V
CF
V
EF
Pin (Note 4)
No Connect
1.5 V
$
100 mV
ECL Mode
LVCMOS Mode
LVTTL Mode (Note 5)
4. Short V
CF
(pin 8) and V
EF
(pin 7).
5. When Operating in LVTTL Mode, the reference voltage can be provided by connecting an external resistor, R
CF
(suggested resistor value
is 2.2 kW
$5%),
between V
CF
and V
EE
pins.
Table 4. DATA INPUT ALLOWED OPERATING VOLTAGE MODE TABLE
CONTROL DATA SELECT INPUTS PINS (D [0:10])
POWER SUPPLY
PECL Mode Operating Range
NECL Mode Operating Range
LVCMOS
YES
N/A
LVTTL
YES
N/A
LVPECL
YES
N/A
LVNECL
N/A
YES
Table 5. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
ESD Protection
(R1)
Human Body Model
Machine Model
Charged Device Model
Pb Pkg
Level 2
−
Value
75 kW
> 2 kV
> 100 V
> 2 kV
Pb−Free Pkg
Level 2
Level 1
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 6)
LQFP−32
QFN−32
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
6. For additional information, see Application Note AND8003/D.
UL 94 V−0 @ 0.125 in
1217 Devices
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4
