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MC14556BCP

4000/14000/40000 SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDIP16, PLASTIC, DIP-16

器件类别:逻辑    逻辑   

厂商名称:Motorola ( NXP )

厂商官网:https://www.nxp.com

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
Motorola ( NXP )
零件包装代码
DIP
包装说明
DIP,
针数
16
Reach Compliance Code
unknown
ECCN代码
EAR99
系列
4000/14000/40000
JESD-30 代码
R-PDIP-T16
JESD-609代码
e0
长度
19.175 mm
负载电容(CL)
50 pF
逻辑集成电路类型
OTHER DECODER/DRIVER
功能数量
2
端子数量
16
最高工作温度
125 °C
最低工作温度
-55 °C
输出极性
INVERTED
封装主体材料
PLASTIC/EPOXY
封装代码
DIP
封装形状
RECTANGULAR
封装形式
IN-LINE
峰值回流温度(摄氏度)
NOT SPECIFIED
传播延迟(tpd)
440 ns
认证状态
Not Qualified
座面最大高度
4.44 mm
最大供电电压 (Vsup)
18 V
最小供电电压 (Vsup)
3 V
标称供电电压 (Vsup)
5 V
表面贴装
NO
技术
CMOS
温度等级
MILITARY
端子面层
Tin/Lead (Sn/Pb)
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
7.62 mm
文档预览
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Binary to 1-of-4
Decoder/Demultiplexer
The MC14555B and MC14556B are constructed with complementary
MOS (CMOS) enhancement mode devices. Each Decoder/Demultiplexer
has two select inputs (A and B), an active low Enable input (E), and four
mutually exclusive outputs (Q0, Q1, Q2, Q3). The MC14555B has the
selected output go to the “high” state, and the MC14556B has the selected
output go to the “low” state. Expanded decoding such as binary–to–hexade-
cimal (1–of–16), etc., can be achieved by using other MC14555B or
MC14556B devices.
Applications include code conversion, address decoding, memory selec-
tion control, and demultiplexing (using the Enable input as a data input) in
digital data transmission systems.
Diode Protection on All Inputs
Active High or Active Low Outputs
Expandable
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
MC14555B
MC14556B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
V
V
– 0.5 to + 18.0
Vin, Vout
Iin, Iout
PD
Tstg
TL
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
±
10
500
– 65 to + 150
260
Input or Output Current (DC or Transient),
per Pin
Power Dissipation, per Package†
Storage Temperature
Lead Temperature (8–Second Soldering)
mA
mW
TA = – 55° to 125°C for all packages.
TRUTH TABLE
Inputs
Enable
E
0
0
0
0
1
Select
B
0
0
1
1
X
A
0
1
0
1
X
0
0
0
1
0
Outputs
MC14555B
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
0
1
MC14556B
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
_
C
_
C
X = Don’t Care
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
“P and D/DW” Packages: – 7.0 mW/C From 65
_
C To 125
_
C Ceramic
“L” Packages: – 12 mW/
_
C From 100
_
C To 125
_
C
BLOCK DIAGRAM
MC14555B
2
3
1
A
B
E
Q0
Q1
Q2
Q3
4
5
6
7
2
3
1
MC14556B
A
B
E
Q0
Q1
Q2
Q3
4
5
6
7
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
v
v
14
13
15
A
B
E
Q0
Q1
Q2
Q3
12
11
10
9
VDD = PIN 16
VSS = PIN 8
14
13
15
A
B
E
Q0
Q1
Q2
Q3
12
11
10
9
REV 3
1/94
©
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
MC14555B MC14556B
1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS)
Characteristic
Symbol
VOL
VDD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
VIH
5.0
10
15
IOH
Source
5.0
5.0
10
15
IOL
5.0
10
15
15
5.0
10
15
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
0.64
1.6
4.2
±
0.1
5.0
10
20
– 2.4
– 0.51
– 1.3
– 3.4
0.51
1.3
3.4
– 4.2
– 0.88
– 2.25
– 8.8
0.88
2.25
8.8
±
0.00001
5.0
0.005
0.010
0.015
±
0.1
7.5
5.0
10
20
– 1.7
– 0.36
– 0.9
– 2.4
0.36
0.9
2.4
±
1.0
150
300
600
mAdc
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
mAdc
Min
– 55
_
C
25
_
C
125
_
C
Max
Min
Typ #
0
0
0
Max
Min
Max
Unit
Vdc
Output Voltage
Vin = VDD or 0
“0” Level
0.05
0.05
0.05
1.5
3.0
4.0
0.05
0.05
0.05
1.5
3.0
4.0
0.05
0.05
0.05
1.5
3.0
4.0
Vdc
“1” Level
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Input Current
Input Capacitance
(Vin = 0)
Quiescent Current
(Per Package)
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
VIL
2.25
4.50
6.75
VOH
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Vdc
Sink
Iin
Cin
IDD
µAdc
pF
µAdc
IT
IT = (0.85
µA/kHz)
f + IDD
IT = (1.70
µA/kHz)
f + IDD
IT = (2.60
µA/kHz)
f + IDD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25
_
C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in
µA
(per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
PIN ASSIGNMENTS
MC14555B
EA
AA
BA
Q0A
Q1A
Q2A
Q3A
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
EB
AB
BB
Q0B
Q1B
Q2B
Q3B
EA
AA
BA
Q0A
Q1A
Q2A
Q3A
VSS
MC14556B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
EB
AB
BB
Q0B
Q1B
Q2B
Q3B
MC14555B MC14556B
2
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS*
(CL = 50 pF, TA = 25
_
C)
Characteristic
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
Propagation Delay Time — A, B to Output
tPLH, tPHL = (1.7 ns/pF) CL + 135 ns
tPLH, tPHL = (0.66 ns/pF) CL + 62 ns
tPLH, tPHL = (0.5 ns/pF) CL + 45 ns
Propagation Delay Time — E to Output
tPLH, tPHL = (1.7 ns/pF) CL + 115 ns
tPLH, tPHL = (0.66 ns/pF) CL + 52 ns
tPLH, tPHL = (0.5 ns/pF) CL + 40 ns
Symbol
tTLH,
tTHL
VDD
5.0
10
15
5.0
10
15
5.0
10
15
Min
Typ #
100
50
40
220
95
70
200
85
65
Max
200
100
80
440
190
140
ns
400
170
130
Unit
ns
tPLH,
tPHL
ns
tPLH,
tPHL
* The formulas given are for the typical characteristics only at 25
_
C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
INPUT E LOW
20 ns
20 ns
90%
50%
10%
VDD
VSS
VDD
VSS
VOH
VOL
20 ns
INPUT B
tPHL
OUTPUT Q3
MC14556B
tTHL
tPLH
OUTPUT Q3
MC14555B
tTLH
90%
50%
10%
INPUT A HIGH, INPUT E LOW
20 ns
90%
50%
10%
tPLH
VDD
VSS
VOH
A INPUTS
(50% DUTY CYCLE)
1
2f
B INPUTS
(50% DUTY CYCLE)
OUTPUT Q1
All 8 outputs connect to respective CL loads.
f in respect to a system clock.
90%
50%
10%
V
tTLH OL
tPHL
VOH
VOL
tTHL
Figure 1. Dynamic Power Dissipation Signal Waveforms
Figure 2. Dynamic Signal Waveforms
LOGIC DIAGRAM
(1/2 of Dual)
*
A
*
B
*
E
*
* Eliminated for MC14555B
Q3
Q2
Q1
Q0
MOTOROLA CMOS LOGIC DATA
MC14555B MC14556B
3
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16
9
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
DIM
A
B
C
D
E
F
G
H
K
L
M
N
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
–––
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0
_
15
_
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
–––
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0
_
15
_
0.51
1.01
–B–
1
8
C
L
–T–
SEATING
PLANE
N
E
F
D
G
16 PL
K
M
J
16 PL
0.25 (0.010)
M
M
T B
S
0.25 (0.010)
T A
S
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0
_
10
_
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0
_
10
_
0.51
1.01
B
1
8
F
S
C
L
–T–
H
G
D
16 PL
SEATING
PLANE
K
J
T A
M
M
0.25 (0.010)
M
MC14555B MC14556B
4
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
_
7
_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
_
7
_
0.229
0.244
0.010
0.019
16
9
–B–
1
8
P
8 PL
0.25 (0.010)
M
B
S
G
F
K
C
–T–
SEATING
PLANE
R
X 45
_
M
D
16 PL
M
J
0.25 (0.010)
T B
S
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,
Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE/Locations Not Listed:
Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
MFAX:
RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609
INTERNET:
http://Design–NET.com
JAPAN:
Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
ASIA/PACIFIC:
Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MOTOROLA CMOS LOGIC DATA
*MC14555B/D*
MC14555B MC14556B
MC14555B/D
5
查看更多>
参数对比
与MC14556BCP相近的元器件有:MC14555BCL、MC14556BCL。描述及对比如下:
型号 MC14556BCP MC14555BCL MC14556BCL
描述 4000/14000/40000 SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDIP16, PLASTIC, DIP-16 4000/14000/40000 SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16 4000/14000/40000 SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDIP16, CERAMIC, DIP-16
是否Rohs认证 不符合 不符合 不符合
厂商名称 Motorola ( NXP ) Motorola ( NXP ) Motorola ( NXP )
零件包装代码 DIP DIP DIP
包装说明 DIP, DIP, DIP,
针数 16 16 16
Reach Compliance Code unknown unknown unknown
ECCN代码 EAR99 EAR99 EAR99
系列 4000/14000/40000 4000/14000/40000 4000/14000/40000
JESD-30 代码 R-PDIP-T16 R-GDIP-T16 R-GDIP-T16
JESD-609代码 e0 e0 e0
长度 19.175 mm 19.495 mm 19.495 mm
负载电容(CL) 50 pF 50 pF 50 pF
逻辑集成电路类型 OTHER DECODER/DRIVER OTHER DECODER/DRIVER OTHER DECODER/DRIVER
功能数量 2 2 2
端子数量 16 16 16
最高工作温度 125 °C 125 °C 125 °C
最低工作温度 -55 °C -55 °C -55 °C
输出极性 INVERTED TRUE INVERTED
封装主体材料 PLASTIC/EPOXY CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED
封装代码 DIP DIP DIP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 IN-LINE IN-LINE IN-LINE
峰值回流温度(摄氏度) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
传播延迟(tpd) 440 ns 440 ns 440 ns
认证状态 Not Qualified Not Qualified Not Qualified
座面最大高度 4.44 mm 5.08 mm 5.08 mm
最大供电电压 (Vsup) 18 V 18 V 18 V
最小供电电压 (Vsup) 3 V 3 V 3 V
标称供电电压 (Vsup) 5 V 5 V 5 V
表面贴装 NO NO NO
技术 CMOS CMOS CMOS
温度等级 MILITARY MILITARY MILITARY
端子面层 Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE
端子节距 2.54 mm 2.54 mm 2.54 mm
端子位置 DUAL DUAL DUAL
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
宽度 7.62 mm 7.62 mm 7.62 mm
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器件捷径:
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ
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