Freescale Semiconductor
Technical Data
Document Number: MC33887
Rev. 13.0, 10/2008
5.0 A H-Bridge with Load
Current Feedback
The 33887 is a monolithic H-Bridge Power IC with a load current
feedback feature making it ideal for closed-loop DC motor control.
The IC incorporates internal control logic, charge pump, gate drive,
and low R
DS(ON)
MOSFET output circuitry. The 33887 is able to
control inductive loads with continuous DC load currents up to 5.0 A,
and with peak current active limiting between 5.2 A and 7.8 A. Output
loads can be pulse width modulated (PWM-ed) at frequencies up to
10 kHz. The load current feedback feature provides a proportional (1/
375th of the load current) constant-current output suitable for
monitoring by a microcontroller’s A/D input. This feature facilitates
the design of closed-loop torque/speed control as well as open load
detection.
A Fault Status output pin reports undervoltage, short circuit, and
overtemperature conditions. Two independent inputs provide polarity
control of two half-bridge totem-pole outputs. Two disable inputs
force the H-Bridge outputs to tri-state (exhibit high impedance).
The 33887 is parametrically specified over a temperature range of
-40°C
≤
T
A
≤
125°C and a voltage range of 5.0 V
≤
V+
≤
28 V.
Operation with voltages up to 40 V with derating of the specifications.
Features
Fully specified operation 5.0 V to 28 V
Limited operation with reduced performance up to 40 V
120 mΩ R
DS(ON)
Typical H-Bridge MOSFETs
TTL/CMOS Compatible Inputs
PWM Frequencies up to 10 kHz
Active Current Limiting (Regulation)
Fault Status Reporting
Sleep Mode with Current Draw
≤50 μA
(Inputs Floating or Set
to Match Default Logic States)
• Pb-Free Packaging Designated by Suffix Codes VW and EK
•
•
•
•
•
•
•
•
Device
MC33887DH/R2
MC33887VW/R2
MC33887AVW/R2
MC33887PNB/R2
MC33887DWB/R2
MCZ33887EK/R2
33887
H-BRIDGE
DH SUFFIX
VW SUFFIX (Pb-FREE)
98ASH70273A
20-PIN HSOP
PNB SUFFIX
98ASA10583D
36-PIN PQFN
Bottom View
DWB SUFFIX
EK SUFFIX (Pb-FREE)
98ASA10506D
54-PIN SOICW-EP
ORDERING INFORMATION
Temperature
Range (T
A
)
Package
20 HSOP
-40°C to 125°C
36 PQFN
54 SOICW-EP
6.0 V
V+
33887
CCP
IN
OUT
OUT
OUT
OUT
OUT
A/D
FS
EN
IN1
IN2
D1
D2
FB
OUT2
PGND
AGND
MOTOR
V+
OUT1
MCU
Figure 1. 33887 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2007 - 2008. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
CCP
VPWR
EN
CHARGE PUMP
8
μ
A
(
EACH
)
5.0 V
REGULATOR
CURRENT
LIMIT,
OVERCURRENT
SENSE &
FEEDBACK
CIRCUIT
OUT1
GATE
DRIVE
OUT2
IN1
IN2
D1
D2
25
μ
A
CONTROL
LOGIC
OVER
TEMPERATURE
UNDERVOLTAGE
FS
FB
AGND
PGND
Figure 2. 33887 Simplified Internal Block Diagram
33887
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
Tab
AGND
FS
IN1
V+
V+
OUT1
OUT1
FB
PGND
PGND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
EN
IN2
D1
CCP
V+
OUT2
OUT2
D2
PGND
PGND
Tab
Figure 3. 33887 Pin Connections
Table 1. 33887 HSOP PIN DEFINITIONS
A functional description of each pin can be found in the
Functional Pin DescriptionS
section,
page 21.
Pin
1
2
Pin Name
AGND
FS
Formal Name
Analog Ground
Fault Status for H-Bridge
Definition
Low-current analog signal ground.
Open drain active LOW Fault Status output requiring a pull-up resistor to
5.0 V.
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
Positive supply connections
Output 1 of H-Bridge.
Current sensing feedback output providing ground referenced 1/375th
(0.00266) of H-Bridge high-side current.
High-current power ground.
Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When D2 is Logic LOW, both outputs are tri-stated.
Output 2 of H-Bridge.
External reservoir capacitor connection for internal charge pump capacitor.
Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
Logic input Enable control of device (i.e., EN logic HIGH = full operation, EN
logic LOW = Sleep Mode).
Exposed pad thermal interface for sinking heat from the device.
Note
Must be DC-coupled to analog ground and power ground via very low
impedance path to prevent injection of spurious signals into IC substrate.
3
4 , 5, 16
6, 7
8
IN1
V+
OUT1
FB
Logic Input Control 1
Positive Power Supply
H-Bridge Output 1
Feedback for H-Bridge
9 – 12
13
PGND
D2
Power Ground
Disable 2
14 , 15
17
18
OUT2
CCP
D1
H-Bridge Output 2
Charge Pump Capacitor
Disable 1
19
20
IN2
EN
Logic Input Control 2
Enable
Tab/Pad
Thermal
Interface
Exposed Pad Thermal
Interface
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Transparent Top View of Package
36
35
34
33
32
31
30
29
CCP
V+
V+
OUT2
OUT2
NC
OUT2
OUT2
NC
D1
IN2
EN
V+
V+
NC
AGND
FS
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
28
27
26
25
24
23
22
21
20
19
NC
D2
PGND
PGND
PGND
PGND
PGND
PGND
FB
NC
Figure 4. 33887 Pin Connections
Table 2. PQFN PIN DEFINITIONS
A functional description of each pin can be found in the
Functional Pin DescriptionS
section,
page 21.
Pin
1, 7, 10, 16,
19, 28, 31
2
3
4
5, 6, 12, 13, 34, 35
8
9
11
14, 15, 17, 18
20
21– 26
27
29, 30, 32, 33
36
Pad
Pin Name
NC
D1
IN2
EN
V+
AGND
FS
IN1
OUT1
FB
PGND
D2
OUT2
CCP
Thermal
Interface
Formal Name
No Connect
Disable 1
Logic Input Control 2
Enable
Positive Power Supply
Analog Ground
Fault Status for H-Bridge
Logic Input Control 1
H-Bridge Output 1
Feedback for H-Bridge
Power Ground
Disable 2
H-Bridge Output 2
Charge Pump Capacitor
Exposed Pad Thermal
Interface
Definition
No internal connection to this pin.
Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
Logic input Enable control of device (i.e., EN logic HIGH = full operation,
EN logic LOW = Sleep Mode).
Positive supply connections.
Low-current analog signal ground.
Open drain active LOW Fault Status output requiring a pull-up resistor to
5.0 V.
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
Output 1 of H-Bridge.
Current feedback output providing ground referenced 1/375th ratio of
H-Bridge high-side current.
High-current power ground.
Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When D2 is Logic LOW, both outputs are tri-stated.
Output 2 of H-Bridge.
External reservoir capacitor connection for internal charge pump
capacitor.
Exposed pad thermal interface for sinking heat from the device.
Note:
Must be DC-coupled to analog ground and power ground via very
low impedance path to prevent injection of spurious signals into IC
substrate.
33887
IN1
V+
V+
OUT1
OUT1
NC
OUT1
OUT1
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
Transparent Top View of Package
PGND
PGND
PGND
PGND
NC
NC
NC
D2
NC
OUT2
OUT2
OUT2
OUT2
NC
V+
V+
V+
V+
NC
NC
NC
NC
CCP
D1
IN2
EN
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
.35
34
33
32
31
30
29
28
PGND
PGND
PGND
PGND
NC
NC
NC
FB
NC
OUT1
OUT1
OUT1
OUT1
NC
V+
V+
V+
V+
NC
NC
NC
NC
IN1
FS
AGND
NC
NC
Figure 5. 33887 Pin Connections
Table 3. SOICW-EP PIN DEFINITIONS
A functional description of each pin can be found in the
Functional Pin DescriptionS
section,
page 21.
Pin
1– 4, 51– 54
5 – 7, 9, 14, 19 – 22,
27 – 29, 33 – 36, 41,
46, 48 – 50
8
Pin Name
PGND
NC
Formal Name
Power Ground
No Connect
High-current power ground.
No internal connection to this pin.
Definition
D2
Disable 2
Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When D2 is Logic LOW, both outputs are tri-stated.
Output 2 of H-Bridge.
Positive supply connections.
External reservoir capacitor connection for internal charge pump
capacitor.
Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
Logic input Enable control of device (i.e., EN logic HIGH = full operation,
EN logic LOW = Sleep Mode).
Low-current analog signal ground.
Open drain active LOW Fault Status output requiring a pull-up resistor to
5.0 V.
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
10 – 13
15 – 18, 37 – 40
23
OUT2
V+
CCP
H-Bridge Output 2
Positive Power Supply
Charge Pump Capacitor
24
D1
Disable 1
25
26
IN2
EN
Logic Input Control 2
Enable
30
31
AGND
FS
Analog Ground
Fault Status for H-Bridge
32
IN1
Logic Input Control 1
33887
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
