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ON Semiconductort
High Slew Rate, Wide
Bandwidth, JFET Input
Operational Amplifiers
These devices are a new generation of high speed JFET input monolithic
operational amplifiers. Innovative design concepts along with JFET
technology provide wide gain bandwidth product and high slew rate.
Well–matched JFET input devices and advanced trim techniques ensure low
input offset errors and bias currents. The all NPN output stage features large
output voltage swing, no deadband crossover distortion, high capacitive
drive capability, excellent phase and gain margins, low open loop output
impedance, and symmetrical source/sink AC frequency response.
This series of devices is available in fully compensated or
decompensated (A
VCL
≤2)
and is specified over a commercial temperature
range. They are pin compatible with existing Industry standard operational
amplifiers, and allow the designer to easily upgrade the performance of
existing designs.
•
Wide Gain Bandwidth: 8.0 MHz for Fully Compensated Devices
Wide Gain Bandwidth:
16 MHz for Decompensated Devices
•
High Slew Rate: 25 V/µs for Fully Compensated Devices
High Slew Rate:
50 V/µs for Decompensated Devices
•
High Input Impedance: 10
12
Ω
MC34080
thru
MC34085
HIGH PERFORMANCE
JFET INPUT
OPERATIONAL AMPLIFIERS
8
1
8
1
P SUFFIX
PLASTIC PACKAGE
CASE 626
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
PIN CONNECTIONS
Offset Null
Inv. Input
Noninv. Input
V
EE
1
2
3
4
-
+
8
7
6
5
NC
V
CC
Output
Offset Null
•
•
•
•
•
Input Offset Voltage: 0.5 mV Maximum (Single Amplifier)
Large Output Voltage Swing: –14.7 V to +14 V for
Large Output Voltage Swing:
V
CC
/V
EE
=
±15
V
Low Open Loop Output Impedance: 30
Ω
@ 1.0 MHz
Low THD Distortion: 0.01%
Excellent Phase/Gain Margins: 55°/7.6 dB for Fully Compensated
Devices
ORDERING INFORMATION
(Single, Top View)
Output 1
Inputs 1
V
EE
1
2
–
3 +
4
8
7
–
+
6
5
V
CC
Output 2
Inputs 2
Op Amp
Function
Single
Dual
Quad
Fully
Compen-
sated
MC34081BD
MC34081BP
MC34082P
MC34084DW
MC34084P
A
VCL
≥2
Compensated
MC34080BD
MC34080BP
MC34083BP
MC34085BDW
MC34085BP
Operating
Temperature
Range
(Dual, Top View)
Package
SO–8
T
A
= 0° to +70°C
Plastic DIP
Plastic DIP
SO–16L
14
1
16
1
T
A
= 0° to +70°C
Plastic DIP
P SUFFIX
PLASTIC PACKAGE
CASE 646
DW SUFFIX
PLASTIC PACKAGE
CASE 751G
(SO–16L)
PIN CONNECTIONS
Output 1
Inputs 1
V
CC
Inputs 2
Output 2
NC
1
2
3
4
5
6
7
8
+
-
+
-
-
+
-
+
16
15
14
13
12
11
10
9
Output 4
Inputs 4
V
EE
Inputs 3
Output 3
NC
Output 1
Inputs 1
V
CC
Inputs 2
Output 2
1
2
3
4
5
6
7
+
-
+
-
-
+
-
+
14
13
12
11
10
9
8
Output 4
Inputs 4
V
EE
Inputs 3
Output 3
1
4
1
4
2
3
2
3
(Quad, Top View)
©
Semiconductor Components Industries, LLC, 2002
1
March, 2002 – Rev. 1
Publication Order Number:
MC34080/D
MC34080 thru MC34085
MAXIMUM RATINGS
Rating
Supply Voltage (from V
CC
to V
EE
)
Input Differential Voltage Range
Input Voltage Range
Output Short Circuit Duration (Note 2)
Operating Ambient Temperature Range
Operating Junction Temperature
Storage Temperature Range
Symbol
V
S
V
IDR
V
IR
t
SC
T
A
T
J
T
stg
Value
+44
(Note 1)
(Note 1)
Indefinite
0 to +70
+125
– 65 to +165
Unit
V
V
V
sec
°C
°C
°C
NOTES:
1. Either or both input voltages must not exceed the magnitude of V
CC
or V
EE
.
2. Power dissipation must be considered to ensure maximum junction temperature
(T
J
) is not exceeded.
Representative Schematic Diagram
(Each Amplifier)
V
CC
200
µA
50
µA
850
µA
Q1
D1
-
Inputs
+
+
Q8
C
C
C
F
+
Q5
Q9
500
50
µA
500
Ω
Q10
R6
Q11
D4
RM
100
µA
300
µA
R3
1.0 k
R4
1.0 k
D3
Q2
Q3
5.0
pF
20
pF
J1
J2
R1
240
Q6
18
R
SC
700
R2
Q7
Output
D2
C
M
3.0
pF
Q4
R7
66 k
V
EE
1
Null Adjust
(MC34080, 081)*
5
*Pins 1 & 5 (MC34080,081) should
not
be directly grounded or connected to V
CC
.
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2
MC34080 thru MC34085
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +15 V, V
EE
= – 15 V, T
A
= T
low
to T
high
[Note 3], unless otherwise noted.)
Characteristics
Input Offset Voltage (Note 4)
Single
T
A
= +25°C
T
A
= 0° to +70°C (MC34080B, MC34081B)
Dual
T
A
= +25°C
T
A
= 0° to +70°C (MC34082, MC34083)
Quad
T
A
= +25°C
T
A
= 0° to +70°C (MC34084, MC34085)
Average Temperature Coefficient of Offset Voltage
Input Bias Current (V
CM
= 0 Note 5)
T
A
= +25°C
T
A
= 0° to +70°C
Input Offset Current (V
CM
= 0 Note 5)
T
A
= +25°C
T
A
= 0° to +70°C
Large Signal Voltage Gain (V
O
=
±10
V, R
L
= 2.0 k)
T
A
= +25°C
T
A
= T
low
to T
high
Output Voltage Swing
R
L
= 2.0 k, T
A
= +25°C
R
L
= 10 k, T
A
= +25°C
R
L
= 10 k, T
A
= T
low to
T
high
R
L
= 2.0 k, T
A
= +25°C
R
L
= 10 k, T
A
= +25°C
R
L
= 10 k, T
A
= T
low to
T
high
Output Short Circuit Current (T
A
= +25°C)
Input Overdrive = 1.0 V, Output to Ground
Source
Sink
Input Common Mode Voltage Range
T
A
= +25°C
Common Mode Rejection Ratio (R
S
≤
10 k, T
A
= +25°C)
Power Supply Rejection Ratio (R
S
= 100
Ω,
T
A
= 25°C)
Power Supply Current
Single
T
A
= +25°C
T
A
= T
low
to T
high
Dual
T
A
= +25°C
T
A
= T
low
to T
high
Quad
T
A
= +25°C
T
A
= T
low
to T
high
Symbol
V
IO
—
—
—
—
—
—
∆V
IO
/∆T
I
IB
—
—
I
IO
—
—
A
VOL
25
15
V
OH
13.2
13.4
13.4
V
OL
—
—
—
13.7
13.9
—
–14.1
–14.7
—
—
—
—
–13.5
–14.1
–14.0
mA
20
20
V
ICR
CMRR
PSRR
I
D
—
—
—
—
—
—
2.5
—
4.9
—
9.7
—
3.4
4.2
6.0
7.5
11
13
70
70
31
28
(V
EE
+4.0) to
(V
CC
– 2.0)
90
86
—
—
—
—
V
dB
dB
mA
80
—
—
—
V
0.02
—
0.1
2.0
nA
V/mV
0.06
—
0.2
4.0
nA
—
0.5
—
1.0
—
6.0
—
10
2.0
4.0
3.0
5.0
12
14
—
µV/°C
Min
Typ
Max
Unit
mV
I
SC
NOTES:
(continued)
T
high
= +70°C for MC34080B
3. T
low
= 0°C for MC34080B
0°C for
MC34081B
+70°C for
MC34081B
0°C for
MC34084
+70°C for
MC34084
0°C for
MC34085
+70°C for
MC34085
4. See application information for typical changes in input offset voltage due to solderability and temperature cycling.
5. Limits at T
A
= +25°C are guaranteed by high temperature (T
high
) testing.
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3
MC34080 thru MC34085
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +15 V, V
EE
= – 15 V, T
A
= +25°C, unless otherwise noted.)
Characteristics
Slew Rate (V
in
= –10 V to +10 V, R
L
= 2.0 kΩ, C
L
= 100 pF)
Compensated
A
V
= +1.0
A
V
= –1.0
Decompensated A
V
= +2.0
A
V
= –1.0
Settling Time (10 V Step, A
V
= –1.0)
To 0.10% (±
1
/
2
LSB of 9–Bits)
To 0.01% (±
1
/
2
LSB of 12–Bits)
Gain Bandwidth Product (f = 200 kHz)
Compensated
Decompensated
Power Bandwidth (R
L
= 2.0 k, V
O
= 20 V
pp
, THD = 5.0%)
Compensated A
V
= +1.0
Decompensated A
V
= – 1.0
Phase Margin (Compensated)
R
L
= 2.0 k
R
L
= 2.0 k, C
L
= 100 pF
Gain Margin (Compensated)
R
L
= 2.0 k
R
L
= 2.0 k, C
L
= 100 pF
Equivalent Input Noise Voltage
R
S
= 100
Ω,
f = 1.0 kHz
Equivalent Input Noise Current (f = 1.0 kHz)
Input Capacitance
Input Resistance
Total Harmonic Distortion
A
V
= +10, R
L
= 2.0 k, 2.0
≤
V
O
≤
20 V
pp
, f = 10 kHz
Channel Separation (f = 10 kHz)
Open Loop Output Impedance (f = 1.0 MHz)
Symbol
SR
20
—
35
—
t
s
—
—
GBW
6.0
12
BWp
—
—
φ
m
—
—
A
m
—
—
e
n
I
n
C
i
r
i
THD
—
Z
o
—
—
—
—
—
—
—
7.6
4.5
30
0.01
5.0
10
12
0.05
120
35
—
—
—
—
—
—
—
—
—
nV/
√
Hz
pA/
√
Hz
pF
Ω
%
dB
Ω
55
39
—
—
400
800
—
—
De-
grees
dB
8.0
16
—
—
kHz
0.72
1.6
—
—
MHz
25
30
50
50
—
—
—
—
µs
Min
Typ
Max
Unit
V/µs
VICR , INPUT COMMON MODE VOLTAGE RANGE (V)
Figure 1. Input Common Mode Voltage Range
versus Temperature
0
-1.0
3.0
2.0
1.0
V
EE
0
-55
-25
0
25
50
75
100
125
V
CC
/V
EE
=
±3.0
V to
±22
V
∆V
IO
= 5.0 mA
100 k
V
CC
IIB , INPUT BIAS CURRENT (pA)
10 k
Figure 2. Input Bias Current
versus Temperature
V
CC
/V
EE
=
±15
V
V
CM
= 0 V
1.0 k
100
10
1.0
-55
-25
0
25
50
75
100
125
T
A
, AMBIENT TEMPERATURE (°C)
T
A
, AMBIENT TEMPERATURE (°C)
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4
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