08[18B8 00:53
From Motorola h4fax Ph: 602-244+591 Fax: 602+444693
To Wolfgang Perto Id
Oznl
Order this data
sheet by MH4171D
*
e
‘.
.
..’
MC3417,MC3517
MC3418,MC3518
CONTINUOUSLY VARIABLE SLOPE
DELTA MODULATOR/DEMODULATOR
Providing
decoding,
secure
the
a
simplified
approach
and
to
digital
speech
encoding/
MC351 7/78
series of
CVSDS
is designed for militay
commercia[
telephone
applications.
both encoding
Functions
and decoding functions.
on the Same Chip with
communication
--
A single IC provides
q
Encode and Decode
a Qigita[
Input
..
L SUFFK
for Selection
/.<3
,t.
!}
@ Utilization
of Compatible
12L – Linear Bipolar Technology
s.?
,:.:\(.\
>*},
i:+t
.:$~::
\/$>
,
~ CMOS Compatible
Digital Output
*J<.,
,..
.’.,
;.,
,<,fy
k.’.
@ Digital Input Threshbld Selectable (VCC/2 reference
,?.!*:,
}
~,
..q
*.$*$.:,,..:,
provided on chip)
,*Y ....
.,
:*\.
.*\i ~~~:.
i..,.,
,,,*.\.~+:$,f-
(General
* MC3417/MC3517
has a
3-Bit
Algorithm
“!{$.**ip$.\$>!.,
,
~-.. ,..;
*
Communication)
J/;,
““
CERAMIC PACUGE
MSE 62O-1O
P
Sumx
PMS~C PACWGE
CASE M-06
DW SUFFIX
P~STIC PAC~GE
CASE 751G-01
SQ-16L
PIN CONNECTIONS
1
Analog
Input
Anal
d
1
[ -)
1
og
Feedback
d
2
(+)
syllabic
Filter
Gain
4
~
4
~
b
15
13
—
Decode
Encoae/
Control
Ref
Input d5
(+}
Fiirer
h
12
P
Dlgttal
O!gital
lnDut
Data
(-}
Threshold
Inp”l (-)
Analog
6
11
Co,ncuaence
—
output
VCC;2
,0
output
4E
7
8
Outout
‘EE
~
P
9
lNF9RMA~ON
Pacha9
Dig]ral
output
;,,
...
e
Analog
output
Ref
input
[.)
Fxlter
Input
[-)
ORD~lNG
Device
I
1
Range
MCM17L
MC~180W
MCWlaL
MCW18P
Ma517L
MB518L
@MoToRou
Ceramic
DIP
PlasticSOIC
Ceramic DIP
PlasticDIP
Ceramic DIP
Ceramic DIP
O“c
+
70”C
to
0% to
O*Cto
O“c
to
- 55-C
10
- 55°C to
+70”C
+ 70’C
+
70”C
+
125%
+ 12WC
DS9488R2
INC.,
19aa
08/1 8B8 00:53
From Motorola Mfax Fh: 602-2444591
Fax: 602-244+6Y3
To Wolfgang Pertold
03Q1
WAX[MUM
[All
RATINGS
nored.)
Value
-0.4
tO
voltages referenced to VEE, TA = 25aC
unless otherwiea
Rat ing
Symbol
Unit
Power
Supply Voltage
Differential
Analeg
Input Volrage
Digilal Threshold
Logic Input
(Clock,
Coincidence
Svllabic
Voltage
vc~
VID
vT~
VLagi~
+18
Vuc
Vdc
Vdc
..,
:,.
C,.
*
5.0
-0.4
-0.4
to
Vcc
to +18
to +18
to
Vol~age
Digital Oata. Encode/
Output
Voltage
Vti
Vdc
Vdc
Vdc
Vdc
mA
Vo(c
on]
VI(SY1)
vi(GC)
vl(Ref)
lRef
-0.4
Filt~r
Input Voltage
Input Voltage
-0.4
to
Vcc
-0.4
Gain Control
Reference
Vcc/2
Vcc
to Vcc
Input Voltage
Current
vc~j2
-1.0
-25
Output
ELECTRICAL C~RACTERISTI~
(Vcc = 12 V, VEE =
Grid. TA = O*C to
Cllantieristic
Power
Power
+7W
for MW17/18,
TA
=
- 55°C to + 125°C i
:ed.)
M@77/Mm517
Typ
1)
Max
16.5
+:$ 12
Mart
16.5
Unit
Vdc
mA
Supply Voltage
Range {Figure
12
Supply Current (figure 1)
(@
Idle Channel]
(Vcc = 5.0 V,
All except MC3418P,DW
(VCC = 5.0 V, MCU18P,DW)
[Vcc = 15 V, All except MU418P.DW)
{V~C = t5 V, MC3418P,DW)
3.7
—
—
IGCR
0.002
3.7
6.0
6.0
5.0
5.5
10
11
Gain Controi Current Ranae (Fiaure 21
Analog Comparator
(Pins
1 and 2)
Input
Range
3.0
1.3
mA
Vdc
VI
(4.75 V = VCC S 16.5 V)
Analog
Output Range {Pin 7)
(4.76 V G“VCC = ~6.5 V. 10 = =5.0
mA)
Ihput
Has
Currents
I
1.3
—
fcc
-1.:
Jcc–1:
1.3
—
Vdc
:.
r,>
(Figure 3)
1.5
1.5
0.5
-0.5
‘,i,
0.25
0.25
0.06
-0.06
1.0
d
(Comparator in Aaive Region)
Analog Input (11)
Analog Feedback {12)
Syllabic Filter Input (131
Reference Input (15)
Inpu? Mset
Analog
—
—
—
1.0
0.3
–
0.3
PA
Current
lnputiAnalog
Feedback
(Comparator in Active Region)
Ill -121 –
?*>,+,
,y-:~ “~.,
0.6
0.2
6.0
—
—
0.05
0.0!
2.0
0.4
0.1
6.0
mV
Figure 3
:~,!
Integrator
Amplifier
115-161
Kgure 4
—
Input Offset Voltage
V/l Converter (Pins 3snd
~%~ Hgure 5
Transconductarr@
.%<,*
VII Convener. ~$p~#:~tiA
Integrator _~@~O
to =5.0 mA Load
Propagatio@jQ~f’*’’% mes (Note 1)
Clock T#~#&<.to Digital
Output
(C$ &\2,$pF
to Grid)
C~~~~~~@ger to Coincidence Output
+,,,@<
~~+w’
‘A 25 PF to Grid)
=
4-0 kQ
tO Vcc)
Voitage —
+,~,.
b. i
&
tpL~
tpHL
tpLH
tp~~
grrr
0.1
1.0
—
—
—
—
0.3
10
1.0
0.8
1.0
0.8
—
0.1
1.0
—
—
0.3
10
1.0
0.8
1.0
0.8
0.12
—
—
2.5
2.5
3.0
2.0
0.25
Vdc
2.5
2.5
3.0
2.0
0.25
C~rrcidence
Output
Low
Logic State
(lOL(Con)
/o~[con)
ioH(con)
—
—
D.tz
—
= 3.0 mAl
Coincidence Output Leakage Curren( —
High Logic State
(voH
=
15 V, O°C s TA s 70nCl
NOW
1. Ail
0.01
0.5
—
0.01
0.5
propagation
delay times measured 507. to
500/.
from the negative going (from
Vcc
to
-0.4
V]
edge of the
clock.
MOTOROLA
@
$emjcanductor
2
Products Inc.
08i18ma
00:53
From Motorola Mfax Ph: 602-2444591 Fax: 602-244~693
{contirtudl
Mc3417/Mc3517
1
—.—–
To Wolfgang Pertoid
04@l
ELECTRIML CHAMCURISTIM
Mc34181Ma518
Max
Vcc -2.0
mn
+1.2
Typ
—
Unit
Vcc -2.0
Vdc
Wn
+?.2
Typ
—
AppIied Digital Threshold Voltage Range
fmm
171
Digital Threshold
Input Current
vTH
!t(th)
(1.2V = v~h= Vcc - 2,QV)
(VIL
applied to Pins 13, 14 and ?5)
[VIM
applied to Pins 13.14 and 15)
Maximum
Output
Integrator
Curr;nt
Amolifier
“
I
16
.“
—
—
= 5.0
—
-lo
5.0
-50
-
—
= 5.0
-lo
5.0
-50
—
—
—
—
3.0
—
mA
VCC/2 Generator
(Source only)
Maximum
output Current
[Ref
ZRef
I
+10
—
—
3.0
—
—
6.0
= 3.5
+10
—
mA
VCC12 Generator
Output
(0 to +10
.
mA)
.- —-. . . . ..
Impedance
VCC12 Generator Tolerance
(4.75 V = VCC = 16.5 V)
Logic Input Voltage (Pins 13, 14 and 15)
Low Logic State
High Loaic State
Dynamic Total Loop ~set
Voltage
(Note 2) — Rgures 3,4 and 5
IGG = 12 wA, vcc = 12 V
TA o 25°C IAII except 3418P,DW}
cr
0/0
Vdc
vi~
Vlu
2V*ff~et
Grtd
vth + 0.4
—
—
-.
(MC3418P,DWI
o“C = TA G +
700C (MC3417/18L}
(MC3418P,DW)
– 55°C < TA s + 125°C (MC3517/18)
iGc =
33@; Vcc = 12
v
~A = 25°C
O°C s TA s + 70°C (MC341 7/18)
- 55’C ~TAs
+ 1Z5°C (MC3517/18)
[GC = ?2 ~, vcc = 5.0 V
T* = 25°C
(AII except M~18p,~w
(MW18P,DW)
O*C % TA < +700C (MC3417/18L)
(MC3418P,DW)
- 55*C ~
TA % +
125*C
{MC3517/18)
iGc =
33 @, Vcc = 5.0 V
TA = 25°C
O°C s TA $ +70°C
(MC3417/la)
–55°C s TA s + 125°C (MC3517/18)
Digital Output Voltage
(IOL = 3.6 mA)
(~OH = -0.35 mA)
Syilatic Pi!ter Appfied Voltage (Pin ,~~
(Rgure 2}
—
—
—
—
—
—
—
—
—
—
—
=2.5
2 se
~=’%:
J ,,,
,,~’~.$,
_
.\t,~
— .tt.,;.,:’~, .+
i~$
.%;. ‘_
- ~i!i~, :+
~:%>,*:.$v
,*_
“~v%h
.,.,
,>,
f?~—
*$
*\:~>
—
—
+ ‘~$<<
~
Ft.,.
—
= 4.0
= 4.5
=5.5
Gnd
vth + 0.4
,~$
,,!X*,,.
.. ,\,.,
~ ~.,
... $,.: t.,
,*A.?*
“’,’!1$
~t:::,
,e$?
. ...
*:$~~
h-
= 0.5
.+ ..,>.
..:. ~t.\.&
=0.5
,, 3:,,.$,,
_
— “$~,$:
$:.!,:\,\:,
* 0.75
...
‘.,y,
..
—
* 0.75
,~,kf~
—
=1.5
*..; ** ....\
“
>,,,,~t~$:’.
~
~~ -“:C’5.O
—
‘i’
—
—
‘*3*y$k 7.5
=10
>...
,.*
—
*1.O
—
—
%?.0
—
—
=1.3
—
—
=1.3
—
& 2.5
& 6.0
= 8.0
510
0.4
—
Vcc
—
vth -0.4
18
vth -0.4
18
rrrv
—
0.1
Vcc - 1.0 Vcc -0.2
+ 3.2
—
—
Vcc– 1.0
+
0.1
0.4
3.2
ICc-a.z
—
—
Vcc
12
1,55
1.58
3.25
8.o
1.45
2;5
10
1.5
—
3.0
12
1.55
8.0
1.4
1.42
—
3.25
2.75
VO{AV*)
—
—
=
100
= 250
—
—
=
100
= 100
= 250
= 280
ltH
—
—
—
—
+5.0
+ 5.0
+ 5.0
—(
—
—
—
+ 5.0
+
5.0
+ 5.0
:.,
-
Digital Oata tnput
Cfock !nput
Encode/Decode
tnvut
—
—
—
I
Clock tnput. VIL =“ 0.4 V
-lo
-360
-36
-72
—
—
—
—
—
—
—
—
-lo
-360
-36
-72
of the analog com~arator
witch current mismatch
16 kHz. For the MC3418/
NO= 2. @narnic
Iotal loop offset (lVoff~etl equals VIO {comparator) {Rgure
3}
minus VIOX (Hgu m
5).
The inpm offset vo[tages
and of
me
integrator amplifier include the effems of input offset current through the input resistors. The slope polarity
aPPears as
an
avera9ev0ita9e
aCrossthe 10 k
integrator resistor. For the MWT71MC3517,
the ctock
frequency
is
M~518,
the clock frequen~ is 32 kHz. Idle channel performance is guaranteed if this dynamic Iotal
Ioop offset is
change in integrator output voltage durrrrg one clock cycle (ramp $!ep size). Laser trimming
Iesg than ~ne.~alf Of the
is used 10 insure good idle channel performance.
I
--—
-- ...-
@
MOTOROLA
Semiconductor Products Inc.
3
08/1 8B8 00:53
From Motorola fvffax Ph: 602-2444591
Fax: 602-2444693
To Wolfgang Pertold
05E1
DEFIN~ONS
AND FUNCTION OF
PINS
...
the encode mode or when the digital data input
. ,,..i
P :
lPin 13) is high in the decode mode. For the opposite
states, Ilnt flows out of Pin 6. Single integration sys-
tems require
a
capacitor and resistor between Pins 6
and 7. Multipole configurations will have different cir-
cuitry. The resistance between Pins 6 and 7 should
always be between 8.0 k~ a nd 13 k~
to
maintain good
idle channel characteristics.
“’: ,“
\.:$,(
l’.l’\:t*;.>.,\:;;*.}
..,. ,,~.
..... ~,.,
.
Wn 7 —
Analag Output
,..”. ..$\,)+,.
This
is the integrator OP amp output. It is+.&~@e
of driving a 600-ohm load referenced t@#~}~
to
amp
+ 6.0 dBrn and can otherwise
be
treate~g~~~~pp
output. Pins 5, 6, and 7 provide
full ac&@,$P’’the inte”
grater op amp for designing int@&&*’
filter net-
works. The slew rate of the in$~rn~a$compensated
integrator op amp is
typically~~~~V/&s.
Pin 7 output
is current limited for both R*~Q~l& of current ffow at
~>$:$ .P*
:Ci
typically 30 mA.
,. *<,:4? ,4.
>
\k.
\“’.:>. . ..’
>,.*.,
,:,..$,},, “
.y:,,.&+\>,
‘ ,.,?..
Pin 8 — VEE
The circuit is de~ped:’b
work in either single or dual
Power SUPP[Y h$~,&hns.
Pin 8 is always connected
to the most n~a~@
supply.
\\+- .>%.*.?.J:,
4:’?
Pin 1 —
Analog
Input
This is
the
analog comparator inverting input where
the voice signal is applied. it may be ac or dc coupled
depending an the appiicatian. If the voice signal is to
be ievel shifted to the internal reference voltage, then
a bias resistor between Pins 1 and 10 is used. The resis-
tor is used
to establish the reference as the new dc
average of the ac coup!ed signal. The analog compar-
ator was designed for low hysteresis (typically less than
0.1 mV) and high gain (typically TO dB).
Pin 2 —
Analog Feedback
This is the noninverting input to the analog signal
comparator within the IC. In an encoder application it
should be connected to the analog output of the errcoder
circuit This may be Pin 7 or a low pass filter output
connected to Pin 7. In a decode circuit Pin 2
is
not
used
and may be tied to VCC/2 on Pin 10, ground
or Ieft
open.
.- .,The analog input comparator .has. bias curren-
of
1.5 WA max, thus the driving impedances of Pins 1 and
2 should be equal to avoid disturbing Che idle
channel
characteristics of the encoder.
Rn
3 —
Syllabic Filter
Thi$ is
the point at which the syllabic filter voltage is
returned to the IC in order to control the integrator step
size. It is an NPN input to an OP amp. The syllabic filter
consists of an RC network
between
Pins 11 and 3. Typ-
ical time constant values of 6.0 ms to 50 ms are used
in voice codecs.
Pin9— ,D#Jgai output
The,r$~gital” ‘output provides the results of the delta
.> .:.., ,
m~&~,~t&Es conversion. it swings between VCC and
~~a@
is CMOS or TTL compatible. Pin 9 is inverting
..l,w$f~spem
to Pin 1 and non-invertina with resoect to
‘X:#~r2. It is clocked on the faIIina edg~ of Pin 14.
The
~pical 10% to 90% rise and fall-tim;s are 250 ns and
Pin
4 —
Gain Control Input
50 ns respectively for VCC = 12 V and CL = 25 pF to
The syllabic filter voltage appears across
Cs
of ths$,,
ground.
syllabic filter and is the voltage between VCC .@N, “~>
-- .$y,:,*,!.*
Q+w
Pin 3. The active voltage to current (V-1) coqyew~
drives Pin 4 to the same voltage at a sle~$$$~k,,~~
Pin 10 — vcc/2 output
An internal low impedance mid-supply reference is
typically 0.5 V/Ws. Thus the current injecteQ,,~@~
4
provided for use of the MC3417/18 in single supply
[IGc) is the syllabic filter voltage dividq~~~$the
Rx
resistance. Figure 7 shows the relatiq+$h$~”’beween
applications. The interns I regulator is a current source
and must be loaded with a resistorto insure its sinking
IGC (x-axis) and the integrating CU@n$-#~t
{Y-aXiS).
The discrepancy, which is mos~ ~QH%@nt at verv low
capability. If a +6.0 dBrno signal is expected across
slope polarity
currents,
is
due to circuitry wl~in’$he
a 600 ohm input bias resistor, then Pin 10 must sink
2.2 VJ600 Q = 3.66 mA. This is only possible if Pin 10
switch which enables trim~$m~:’$~~ a iow total loop
sources 3.66 mA into a resistor normally” and will
offset. The Rx resistor is theh~.$~ed to adjust the 10oP
source only the difference under peak
load.
The ref-
gain of the codec, but @~,uld be no larger than 5.0 k~
erence load resistor is chosen accordingly. A 0.1 PF
to maintain stability. $~~$$F’&
‘~l:.. \
.. .‘.li+,
bypass capacitor from Pin 10 to VEE is also recom-
{k<,....*...;
.
Pin 5 —
Referen@,~~t
mended. The VCC/2 reference is capable of sourcing
This pin is..f&@$#tinverting
inPut of the in1e9rator
10 mA and can be used as a reference
elsewhere in
amplifier. It @“uRq’#toreference the dc level of the output
the system circuitry.
signal. lg$~~$s~oder circuit it must reference the same
voltagez~~~m 1 and is tied to Pin 10.
Pin 11 —
Coincidence Output
.,,\~
~‘,~.$>
,,
.+t.i???:~{
The
duty cycle
of
this pin is proportional to the voltage
~:,%..,8
,t\t\’
Pin 6 ~
Filter input
across CS. The coincidence output will be low whenever
This-inverting op amp input is used to connect the
the content
of
the internal shift register is all 1s or all
integrator externai components. The integrating cur-
0s. In the MC3417 the register is 3 bits long while the
rent (llnt) flows into Pin 6when the analog input (Pin 1)
MC3418 contains a 4 bit register. Pin 11 is an open col-
is high with respect to the analog feedback (Pin 2) in
lector of an NPN device and requires a pull-up resistor.
c
..
‘. ,.*
.... .
..
.....
c
Semiconductor
4
Products
inc.
oa/lam8 00:53
From Motorola Mfax Fh: 602-244%591
Fax: 602-2444693
10 Wolfgang Pertold
06Q1
If the
syllabic filter is to have equal charge and discharge
time constants,
the value of RF should be much less
than Rs. In systems requiring different charge
and dis-
tained
for 0.5 KS before and after the clock trigger for
proper clocking.
Pin 14 — CJockInput
The clock
input determines the data rate of the
codec circuit.
A 32K bit rate
requires a 32 kHz clock.
The switching threshold of the clock input is set by
Pin 12. The
shift register circuit toggles
on the
falling
width for a
edge of the clock input.
The minimum
positive-going
pulse on the clock input ~&&~~~$O
ns,
whereas for a negative-goiag
pulse, it ~x.~,~~i?~.
,.* ,,>’
*<$. /4
,:,.{,C !i
.\k,.
charge constants, the charging constant is RSCS while
the decaying
constant is
(Rs + Rp)CS.
Thus longer
decays are easily achievable.
The NPN device
should
not ba required to sink more than 3.0 mA in any con-
figuration.
The typical 10% to 9070 rise and fall times
are 200 ns and 100 ns respectively for RL = 4.0 k~ to
+12
V and CL = 25
pF to ground.
Pin ?2 — Dig~al Threshold
This input sets the switching threshold for
Pins 13,
14, and 15. It is intended to aid in interfacing different
logic families without efiernal parts. Often it is corr-
ected
to the VC~/2 reference for
CMOS
interface or can
interface.
be biased two diode drops
above VEE
for ~L
.-
Pin 13 —
Digital
Data Input
In a decode application, the digital data stream is
applied to Pin 13. (n an @ncdder it may be unused or
may be
used to transmit
Pin 9. When
flop is formed
signaling message
under the
control of Pin 15. It is an inverting input with respect to
Pins 9 and 13 are connected, a toggle fiip-
and a forced idle channel pattern can be
,
‘\+ ,,:~,:.:>~.
Pin 15 — Encodemeeode
,,$!?..$
This pin controls the connectia~$w$~analog
input
comparator and the digital in@$’cb%parator
to the
internal shift register. If hig@$*~~~.,&sult of the analog
comparison will be clocked ‘~~o,,~e register on the fall-
ing edge at Pin 14. If lq~/~he’’~gital
input state will be
entered. This allows ~$~ae
IC as an encoder/decoder
or simplex codec @~o&
external pa~. Furthermore,
it allows non-voi<~~@rns
to be forced onto the trans-
mission
line tti~~~
Pin 13 in an encoder,
....&$&...:~~.
The .$~%~h SUPD[Y range
is from
Pin
16—$” ‘+’
w:”
4.75 to 16.5
volts
transmitted. The digital data input level should be main-
FIGURE Z - lGcR, GAIN CONTROL RANGE
1Int -
INTEGRATING CURRENT
and
v
cc
?
CVSD
MC3517
‘=3518
i~c
13
Rx
4
0,7
MF
=
12
11
k
Note:
Digital
11
“
MC3517
‘C35’8
Oata
Input
5
12
10 k
6
11
~:A
Cvso
,3
Digital
a.
05
=
~,
7
10 “’
‘
+o.lf16
s
9
=
Digital
0
Outout
OutQut
= Digits\
Oata
Input
“ For static
testing,
the clock
to obtain
is onlv
necesmrv
stete for
for
inpuz,
preconditioning
proper
a given
MOTOROLA
@
.— ..-. .
Semiconductor Products Inc.
5
—
