MC74HC4051A,
MC74HC4052A,
MC74HC4053A
Analog Multiplexers/
Demultiplexers
High−Performance Silicon−Gate CMOS
The MC74HC4051A, MC74HC4052A and MC74HC4053A utilize
silicon−gate CMOS technology to achieve fast propagation delays,
low ON resistances, and low OFF leakage currents. These analog
multiplexers/demultiplexers control analog voltages that may vary
across the complete power supply range (from V
CC
to V
EE
).
The HC4051A, HC4052A and HC4053A are identical in pinout to
the metal−gate MC14051AB, MC14052AB and MC14053AB. The
Channel−Select inputs determine which one of the Analog
Inputs/Outputs is to be connected, by means of an analog switch, to the
Common Output/Input. When the Enable pin is HIGH, all analog
switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors they are compatible with LSTTL
outputs.
These devices have been designed so that the ON resistance (R
on
) is
more linear over input voltage than R
on
of metal−gate CMOS analog
switches.
For a multiplexer/demultiplexer with injection current protection,
see HC4851A and HC4852A.
Features
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SOIC−16 WIDE
DW SUFFIX
CASE 751G
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
1
QFN16
MN SUFFIX
CASE 485AW
MARKING DIAGRAMS
16
HC405xA
AWLYWWG
1
1
SOIC−16 WIDE
16
HC40
5xA
ALYWG
G
1
TSSOP−16
x
A
WL, L
YY, Y
WW, W
G or
G
= 1, 2 or 3
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
4051
ALYWG
G
QFN16
SOIC−16
16
HC405xAG
AWLYWW
•
•
•
•
•
•
•
•
•
•
•
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
Analog Power Supply Range (V
CC
− V
EE
) = 2.0 to 12.0 V
Digital (Control) Power Supply Range (V
CC
− GND) = 2.0 to 6.0 V
Improved Linearity and Lower ON Resistance Than Metal−Gate
Counterparts
Low Noise
In Compliance with the Requirements of JEDEC Standard No. 7A
Chip Complexity: HC4051A − 184 FETs or 46 Equivalent Gates
HC4052A − 168 FETs or 42 Equivalent Gates
HC4053A − 156 FETs or 39 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR−Free and are RoHS
Compliant
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
©
Semiconductor Components Industries, LLC, 2017
1
January, 2017 − Rev. 9
Publication Order Number:
MC74HC4051A/D
MC74HC4051A, MC74HC4052A, MC74HC4053A
FUNCTION TABLE − MC74HC4051A
LOGIC DIAGRAM
MC74HC4051A
Single−Pole, 8−Position Plus Common Off
X0
14
X1
15
X2
ANALOG
12
MULTIPLEXER/
INPUTS/ X3
DEMULTIPLEXER
OUTPUTS X4
1
5
X5
2
X6
4
X7
11
A
CHANNEL
10
B
SELECT
9
INPUTS
C
6
ENABLE
PIN 16 = V
CC
PIN 7 = V
EE
PIN 8 = GND
13
Control Inputs
Enable
L
L
L
L
L
L
L
L
H
Select
C
B
A
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
ON Channels
X0
X1
X2
X3
X4
X5
X6
X7
NONE
X = Don’t Care
3
X
COMMON
OUTPUT/
INPUT
Pinout: MC74HC4051A
(Top View)
V
CC
16
X2
15
X1
14
X0
13
X3
12
A
11
B
10
C
9
1
X4
2
X6
3
X
4
X7
5
X5
6
7
Enable V
EE
8
GND
FUNCTION TABLE − MC74HC4052A
LOGIC DIAGRAM
MC74HC4052A
Double−Pole, 4−Position Plus Common Off
X0
14
X1
15
X2
11
X3
Y0
Y1
Y2
Y3
A
B
1
5
2
4
10
9
6
12
Control Inputs
Enable
L
L
L
L
H
X = Don’t Care
Select
B
A
L
L
H
H
X
L
H
L
H
X
ON Channels
Y0
Y1
Y2
Y3
NONE
X0
X1
X2
X3
X SWITCH
13
X
COMMON
OUTPUTS/INPUTS
ANALOG
INPUTS/OUTPUTS
Y SWITCH
3
Y
Pinout: MC74HC4052A
(Top View)
PIN 16 = V
CC
PIN 7 = V
EE
PIN 8 = GND
V
CC
16
X2
15
X1
14
X
13
X0
12
X3
11
A
10
B
9
CHANNEL‐SELECT
INPUTS
ENABLE
1
Y0
2
Y2
3
Y
4
Y3
5
Y1
6
7
8
GND
Enable V
EE
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2
MC74HC4051A, MC74HC4052A, MC74HC4053A
FUNCTION TABLE − MC74HC4053A
LOGIC DIAGRAM
MC74HC4053A
Triple Single−Pole, Double−Position Plus Common Off
X0
13
X1
Y0
1
Y1
Z0
3
Z1
A
10
CHANNEL‐SELECT
B
INPUTS
9
C
6
ENABLE
11
5
2
12
14
Control Inputs
Enable
L
L
L
L
L
L
L
L
H
C
L
L
L
L
H
H
H
H
X
Select
B
A
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
ON Channels
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
NONE
X0
X1
X0
X1
X0
X1
X0
X1
X SWITCH
X
ANALOG
INPUTS/OUTPUTS
Y SWITCH
15
Y
COMMON
OUTPUTS/INPUTS
Z SWITCH
4
Z
X = Don’t Care
PIN 16 = V
CC
PIN 7 = V
EE
PIN 8 = GND
Pinout: MC74HC4053A
(Top View)
V
CC
16
Y
15
X
14
X1
13
X0
12
A
11
B
10
C
9
NOTE: This device allows independent control of each switch.
Channel−Select Input A controls the X−Switch, Input B controls
the Y−Switch and Input C controls the Z−Switch
1
Y1
2
Y0
3
Z1
4
Z
5
Z0
6
7
8
GND
Enable V
EE
MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
IS
V
in
I
P
D
T
stg
T
L
Parameter
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to V
EE
)
Value
–0.5 to +7.0
–0.5 to +14.0
–7.0 to +5.0
V
EE
− 0.5 to
V
CC
+ 0.5
–0.5 to V
CC
+ 0.5
±25
SOIC Package†
TSSOP Package†
500
450
–65 to +150
260
Unit
V
V
V
V
mA
mW
_C
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Negative DC Supply Voltage (Referenced to GND)
Analog Input Voltage
Digital Input Voltage (Referenced to GND)
DC Current, Into or Out of Any Pin
Power Dissipation in Still Air,
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
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3
MC74HC4051A, MC74HC4052A, MC74HC4053A
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
EE
V
IS
V
in
V
IO
*
T
A
t
r
, t
f
Positive DC Supply Voltage
Negative DC Supply Voltage, Output (Referenced to GND)
Analog Input Voltage
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature Range, All Package Types
Input Rise/Fall Time
(Channel Select or Enable Inputs)
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
–55
0
0
0
0
Parameter
(Referenced to GND)
(Referenced to V
EE
)
Min
2.0
2.0
−6.0
V
EE
GND
Max
6.0
12.0
GND
V
CC
V
CC
1.2
+125
1000
600
500
400
Unit
V
V
V
V
V
_C
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
*For voltage drops across switch greater than 1.2 V (switch on), excessive V
CC
current may be drawn; i.e., the current out of the switch may
contain both V
CC
and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS — Digital Section
(Voltages Referenced to GND) V
EE
= GND, Except Where Noted
Symbol
V
IH
Parameter
Minimum High−Level Input Voltage,
Channel−Select or Enable Inputs
Condition
R
on
= Per Spec
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
6.0
Guaranteed Limit
−55 to 25°C
1.50
2.10
3.15
4.20
0.5
0.9
1.35
1.8
±
0.1
≤85°C
1.50
2.10
3.15
4.20
0.5
0.9
1.35
1.8
±
1.0
≤125°C
1.50
2.10
3.15
4.20
0.5
0.9
1.35
1.8
±
1.0
Unit
V
V
IL
Maximum Low−Level Input Voltage,
Channel−Select or Enable Inputs
R
on
= Per Spec
V
I
in
I
CC
Maximum Input Leakage Current,
Channel−Select or Enable Inputs
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND,
V
EE
= − 6.0 V
Channel Select, Enable and
V
EE
= GND
V
IS
= V
CC
or GND;
V
IO
= 0 V
V
EE
= − 6.0
mA
mA
6.0
6.0
1
4
10
40
20
80
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MC74HC4051A, MC74HC4052A, MC74HC4053A
DC CHARACTERISTICS — Analog Section
Guaranteed Limit
Symbol
R
on
Parameter
Maximum “ON” Resistance
Condition
V
in
= V
IL
or V
IH
; V
IS
= V
CC
to
V
EE
; I
S
≤
2.0 mA
(Figures 1, 2)
V
in
= V
IL
or V
IH
; V
IS
= V
CC
or
V
EE
(Endpoints); I
S
≤
2.0 mA
(Figures 1, 2)
DR
on
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Maximum Off−Channel Leakage
Current, Any One Channel
V
in
= V
IL
or V
IH
;
V
IS
= 1/2 (V
CC
− V
EE
);
I
S
≤
2.0 mA
V
in
= V
IL
or V
IH
;
V
IO
= V
CC
− V
EE
;
Switch Off (Figure 3)
V
CC
4.5
4.5
6.0
4.5
4.5
6.0
4.5
4.5
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
V
EE
0.0
− 4.5
− 6.0
0.0
− 4.5
− 6.0
0.0
− 4.5
− 6.0
− 6.0
− 6.0
− 6.0
− 6.0
− 6.0
− 6.0
− 6.0
−55 to 25°C
190
120
100
150
100
80
30
12
10
0.1
0.2
0.1
0.1
0.2
0.1
0.1
≤85°C
240
150
125
190
125
100
35
15
12
0.5
2.0
1.0
1.0
2.0
1.0
1.0
≤125°C
280
170
140
230
140
115
40
18
14
1.0
4.0
2.0
2.0
4.0
2.0
2.0
mA
W
Unit
W
I
off
mA
Maximum Off−ChannelHC4051A V
in
= V
IL
or V
IH
;
Leakage Current,
HC4052A V
IO
= V
CC
− V
EE
;
Common Channel
HC4053A Switch Off (Figure 4)
I
on
Maximum On−ChannelHC4051A V
in
= V
IL
or V
IH
;
Leakage Current,
HC4052A Switch−to−Switch =
Channel−to−Channel HC4053A V
CC
− V
EE
; (Figure 5)
AC CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbol
t
PLH
,
t
PHL
Parameter
Maximum Propagation Delay, Channel−Select to Analog Output
(Figure 9)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
−55 to 25°C
270
90
59
45
40
25
12
10
160
70
48
39
245
115
49
39
10
35
130
80
50
1.0
≤85°C
320
110
79
65
60
30
15
13
200
95
63
55
315
145
69
58
10
35
130
80
50
1.0
≤125°C
350
125
85
75
70
32
18
15
220
110
76
63
345
155
83
67
10
35
130
80
50
1.0
Unit
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
ns
C
in
C
I/O
Maximum Input Capacitance, Channel−Select or Enable Inputs
Maximum Capacitance
(All Switches Off)
Analog I/O
Common O/I: HC4051A
HC4052A
HC4053A
Feed−through
pF
pF
Typical @ 25°C, V
CC
= 5.0 V, V
EE
= 0 V
C
PD
Power Dissipation Capacitance (Figure 13)*
HC4051A
HC4052A
HC4053A
45
80
45
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
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