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MC74HCT157AN

Quad 2-Input Data Selector/Multiplexer with LSTTL-Compatible Inputs

器件类别:逻辑    逻辑   

厂商名称:Motorola ( NXP )

厂商官网:https://www.nxp.com

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
Motorola ( NXP )
包装说明
DIP, DIP16,.3
Reach Compliance Code
unknow
系列
HCT
JESD-30 代码
R-PDIP-T16
JESD-609代码
e0
长度
19.175 mm
负载电容(CL)
50 pF
逻辑集成电路类型
MULTIPLEXER
最大I(ol)
0.004 A
功能数量
4
输入次数
2
输出次数
1
端子数量
16
最高工作温度
125 °C
最低工作温度
-55 °C
输出极性
TRUE
封装主体材料
PLASTIC/EPOXY
封装代码
DIP
封装等效代码
DIP16,.3
封装形状
RECTANGULAR
封装形式
IN-LINE
峰值回流温度(摄氏度)
NOT SPECIFIED
电源
5 V
Prop。Delay @ Nom-Su
41 ns
传播延迟(tpd)
56 ns
认证状态
Not Qualified
座面最大高度
4.44 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
NO
技术
CMOS
温度等级
MILITARY
端子面层
Tin/Lead (Sn/Pb)
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
7.62 mm
文档预览
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-Input Data
Selector/Multiplexer with
LSTTL-Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT157A is identical in pinout to the LS157. This device may
be used as a level converter for interfacing TTL or NMOS outputs to High
Speed CMOS inputs.
This device routes 2 nibbles (A or B) to a single port (Y) as determined by
the Select input. The data is presented at the outputs in noninverted form. A
high level on the Output Enable input sets all four Y outputs to a low level.
The HCT157A is similar in function to the HC257 which has 3–state
outputs.
Output Drive Capability: 10 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
µA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 102 FETs or 25.5 Equivalent Gates
LOGIC DIAGRAM
A0
NIBBLE
A INPUTS
A1
A2
A3
B0
NIBBLE
B INPUTS
B1
B2
B3
2
5
11
14
4
3
6
10
13
PIN 16 = VCC
PIN 8 = GND
SELECT
OUTPUT ENABLE
1
15
7
9
12
Y0
Y1
Y2
Y3
DATA
OUTPUTS
MC74HCT157A
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
1
16
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC74HCTXXXAN
MC74HCTXXXAD
Plastic
SOIC
PIN ASSIGNMENT
SELECT
A0
B0
Y0
A1
B1
Y1
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
OUTPUT
ENABLE
A3
B3
Y3
A2
B2
Y2
FUNCTION TABLE
Inputs
Output
Enable
H
L
L
Select
X
L
H
Outputs
Y0 – Y3
L
A0 – A3
B0 – B3
Design Criteria
Value
25.5
1.5
Unit
ea
ns
X = don’t care
A0 – A3, B0 – B3 = the levels
of the respective Data–Word
Inputs.
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Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
0.005
µW
pJ
0.0075
* Equivalent to a two input NAND gate.
2/97
©
Motorola, Inc. 1997
1
REV 7
MC74HCT157A
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MAXIMUM RATINGS*
Symbol
VCC
Vin
Parameter
Value
Unit
V
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5
±
20
±
25
±
50
750
500
Vout
Iin
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
mA
mA
mA
Iout
DC Output Current, per Pin
ICC
PD
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air
Storage Temperature
Plastic DIP†
SOIC Package†
mW
Tstg
TL
– 65 to + 150
260
_
C
_
C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/
_
C from 65
_
to 125
_
C
SOIC Package: – 7 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
4.5
0
Max
5.5
Unit
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
Vin, Vout
TA
VCC
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
– 55
0
+ 125
500
_
C
ns
tr, tf
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
S b l
VIH
VIL
Parameter
P
Test C di i
T
Conditions
VCC
V
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
– 55 to
25
_
C
2.0
2.0
0.8
0.8
44
5.4
v
85
_
C
v
125
_
C
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
3.7
0.1
0.1
0.4
Unit
U i
V
V
V
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20
µA
v
v
v
v
v
v
Maximum Low–Level Input
Voltage
Vout 0.1 V or VCC – 0.1 V
|Iout|
20 mA
Vin = VIH or VIL
|Iout|
20 mA
Vin = VIH or VIL
|Iout|
4.0 mA
Vin = VIH or VIL
|Iout|
20
µA
Vin = VIH or VIL
|Iout|
4.0 mA
VOH
Minimum High–Level Output
Voltage
3.98
0.1
0.1
3.84
0.1
0.1
VOL
Maximum Low–Level Output
Voltage
V
0.26
0.33
Iin
Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Vin = VCC or GND
Iout = 0
µA
±
0.1
4.0
±
1.0
40
±
1.0
160
µA
µA
ICC
∆I
CC
Additional Quiescent Supply
Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0
µA
– 55
_
C
2.9
25
_
C to 125
_
C
2.4
5.5
55
mA
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HCT157A
AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0 V
±
10%, CL = 50 pF, Input tr = tf = 6.0 ns)
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Guaranteed Limit
Symbol
S b l
tPLH,
tPHL
tPLH,
tPHL
tPLH,
tPHL
tTLH,
tTHL
tr, tf
Parameter
P
– 55 to
25
_
C
27
37
30
15
v
85
_
C
34
46
38
19
v
125
_
C
41
56
45
22
Unit
U i
ns
ns
ns
ns
ns
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 4)
Maximum Propagation Delay, Select to Output Y
(Figures 2 and 4)
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 4)
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Rise and Fall Time
500
500
500
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
64
CPD
Power Di i i C
P
Dissipation Capacitance (P T
i
(Per Transceiver Ch
i
Channel)*
l)*
pF
F
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
INPUTS
A0, A1, A2, A3 (Pins 2, 5, 11, 14)
Nibble A inputs. The data present on these pins is trans-
ferred to the outputs when the Select input is at a low level
and the Output Enable input is at a low level. The data is
presented to the outputs in noninverted form.
B0, B1, B2, B3 (Pins 3, 6, 10, 13)
Nibble B inputs. The data present on these pins is trans-
ferred to the outputs when the Select input is at a high level
and the Output Enable input is at a low level. The data is
presented to the outputs in noninverted form.
OUTPUTS
Y0, Y1, Y2, Y3 (Pins 4, 7, 9, 12)
Data outputs. The selected input Nibble is presented at
these outputs when the Output Enable input is at a low level.
The data is presented to the outputs in noninverted form. For
the Output Enable input at a high level, the outputs are at a
low level.
CONTROL INPUTS
Select (Pin 1)
Nibble select. This input determines the data word to be
transferred to the outputs. A low level on this input selects
the A inputs and a high level selects the B inputs.
Output Enable (Pin 15)
Output Enable input. A low level on this input allows the
selected input data to be presented at the outputs. A high
level on this input sets all outputs to a low level.
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
MC74HCT157A
EXPANDED LOGIC DIAGRAM
A0
B0
A1
B1
NIBBLE
INPUTS
A2
B2
A3
B3
OUTPUT ENABLE
SELECT
2
3
5
6
11
10
14
13
12 Y3
9
Y2
7
Y1
DATA
OUTPUTS
4
Y0
SWITCHING WAVEFORMS
tr
INPUT A OR B
tPLH
OUTPUT Y
tTLH
90%
1.3 V
10%
tTHL
2.7 V
1.3 V
0.3 V
tPHL
tf
tr
3V
SELECT
GND
tPLH
OUTPUT Y
90%
1.3 V
10%
tTLH
tTHL
2.7 V
1.3 V
0.3 V
tPHL
tf
3V
GND
Figure 1.
Figure 2.
TEST POINT
tr
OUTPUT ENABLE
tPHL
OUTPUT Y
tTHL
90%
1.3 V
10%
tTLH
* Includes all probe and jig capacitance
2.7 V
1.3 V
0.3 V
tPLH
tf
VCC
GND
OUTPUT
DEVICE
UNDER
TEST
CL*
Figure 3.
Figure 4. Test Circuit
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HCT157A
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
B
1
8
–A
16
9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
10°
10°
0.020 0.040
0.51
1.01
F
S
C
L
–T
H
G
D
16 PL
0.25 (0.010)
M
SEATING
PLANE
K
J
T A
M
M
–A
16
9
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–B
1
8
P
8 PL
0.25 (0.010)
M
B
M
G
F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0.229 0.244
0.010 0.019
K
C
–T
SEATING
PLANE
R
X 45°
M
D
16 PL
0.25 (0.010)
M
J
T
B
S
A
S
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High–Speed CMOS Logic Data
DL129 — Rev 6
5
MC74HCT157A/D
MOTOROLA
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参数对比
与MC74HCT157AN相近的元器件有:MC74HCT157A、MC74HCT157AD。描述及对比如下:
型号 MC74HCT157AN MC74HCT157A MC74HCT157AD
描述 Quad 2-Input Data Selector/Multiplexer with LSTTL-Compatible Inputs Quad 2-Input Data Selector/Multiplexer with LSTTL-Compatible Inputs Quad 2-Input Data Selector/Multiplexer with LSTTL-Compatible Inputs
是否Rohs认证 不符合 - 不符合
厂商名称 Motorola ( NXP ) - Motorola ( NXP )
包装说明 DIP, DIP16,.3 - SOP,
Reach Compliance Code unknow - unknow
系列 HCT - HCT
JESD-30 代码 R-PDIP-T16 - R-PDSO-G16
JESD-609代码 e0 - e0
长度 19.175 mm - 9.9 mm
负载电容(CL) 50 pF - 50 pF
逻辑集成电路类型 MULTIPLEXER - MULTIPLEXER
功能数量 4 - 4
输入次数 2 - 2
输出次数 1 - 1
端子数量 16 - 16
最高工作温度 125 °C - 125 °C
最低工作温度 -55 °C - -55 °C
输出极性 TRUE - TRUE
封装主体材料 PLASTIC/EPOXY - PLASTIC/EPOXY
封装代码 DIP - SOP
封装形状 RECTANGULAR - RECTANGULAR
封装形式 IN-LINE - SMALL OUTLINE
峰值回流温度(摄氏度) NOT SPECIFIED - NOT SPECIFIED
传播延迟(tpd) 56 ns - 56 ns
认证状态 Not Qualified - Not Qualified
座面最大高度 4.44 mm - 1.75 mm
最大供电电压 (Vsup) 5.5 V - 5.5 V
最小供电电压 (Vsup) 4.5 V - 4.5 V
标称供电电压 (Vsup) 5 V - 5 V
表面贴装 NO - YES
技术 CMOS - CMOS
温度等级 MILITARY - MILITARY
端子面层 Tin/Lead (Sn/Pb) - Tin/Lead (Sn/Pb)
端子形式 THROUGH-HOLE - GULL WING
端子节距 2.54 mm - 1.27 mm
端子位置 DUAL - DUAL
处于峰值回流温度下的最长时间 NOT SPECIFIED - NOT SPECIFIED
宽度 7.62 mm - 3.9 mm
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