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MC74LCX573
Low-Voltage CMOS
Octal Transparent Latch
Flow Through Pinout
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The MC74LCX573 is a high performance, non−inverting octal
transparent latch operating from a 2.3 to 3.6 V supply. High
impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A V
I
specification of 5.5 V allows
MC74LCX573 inputs to be safely driven from 5.0 V devices.
The MC74LCX573 contains 8 D−type latches with 3−state standard
outputs. When the Latch Enable (LE) input is HIGH, data on the Dn
inputs enters the latches. In this condition, the latches are transparent,
i.e., a latch output will change state each time its D input changes.
When LE is LOW, the latches store the information that was present
on the D inputs a setup time preceding the HIGH−to−LOW transition
of LE. The 3−state standard outputs are controlled by the Output
Enable (OE) input. When OE is LOW, the standard outputs are
enabled. When OE is HIGH, the standard outputs are in the high
impedance state, but this does not interfere with new data entering into
the latches. The LCX573 flow through design facilitates easy PC
board layout.
Features
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MARKING
DIAGRAMS
20
LCX573
AWLYYWWG
1
SOIC−20 WB
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
A
L, WL
Y, YY
W, WW
G or
G
=
=
=
=
=
LCX
573
ALYWG
G
•
•
•
•
•
•
•
•
Designed for 2.3 to 3.6 V V
CC
Operation
5.0 V Tolerant
−
Interface Capability With 5.0 V TTL Logic
Supports Live Insertion and Withdrawal
I
OFF
Specification Guarantees High Impedance When V
CC
= 0 V
LVTTL Compatible
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Assembly Location
Wafer Lot
Year
Work Week
Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
Near Zero Static Supply Current in All Three Logic States (10
mA)
Substantially Reduces System Power Requirements
•
Latchup Performance Exceeds 500 mA
•
ESD Performance:
♦
Human Body Model >2000 V
♦
Machine Model >200 V
•
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
©
Semiconductor Components Industries, LLC, 2013
January, 2013
−
Rev. 12
1
Publication Order Number:
MC74LCX573/D
MC74LCX573
OE
LE
1
11
2
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
19
O0
V
CC
20
O0
19
O1
18
O2
17
O3
16
O4
15
O5
14
O6
13
O7
12
LE
11
D0
Q
D1
3
Q
18
O1
D2
1
OE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10
GND
D3
4
Q
17
O2
Figure 1. Pinout
(Top View)
5
16
Q
O3
PIN NAMES
Pins
OE
LE
D0−D7
O0−O7
Function
Output Enable Input
Latch Enable Input
Data Inputs
3−State Latch Outputs
D4
6
Q
15
O4
D5
7
14
Q
O5
D6
8
Q
13
O6
D7
9
Q
12
O7
Figure 2. Logic Diagram
TRUTH TABLE
Inputs
OE
L
L
L
L
L
H
H
H
H
H
LE
H
H
L
L
L
L
H
H
L
L
Dn
H
L
h
l
X
X
H
L
h
l
Outputs
On
H
L
H
L
NC
Z
Z
Z
Z
Z
Operating Mode
Transparent (Latch Disabled); Read Latch
Latched (Latch Enabled) Read Latch
Hold; Read Latch
Hold; Disabled Outputs
Transparent (Latch Disabled); Disabled Outputs
Latched (Latch Enabled); Disabled Outputs
H = High Voltage Level;
h = High Voltage Level One Setup Time Prior to the Latch Enable High−to−Low Transition
L = Low Voltage Level
l = Low Voltage Level One Setup Time Prior to the Latch Enable High−to−Low Transition
NC = No Change, State Prior to the Latch Enable High−to−Low Transition
X = High or Low Voltage Level or Transitions are Acceptable
Z = High Impedance State
For I
CC
Reasons DO NOT FLOAT Inputs
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2
MC74LCX573
MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current Per Supply Pin
DC Ground Current Per Ground Pin
Storage Temperature Range
Value
−0.5
to +7.0
−0.5
≤
V
I
≤
+7.0
−0.5
≤
V
O
≤
+7.0
−0.5
≤
V
O
≤
V
CC
+ 0.5
−50
−50
+50
±50
±100
±100
−65
to +150
Output in 3−State
Output in HIGH or LOW State (Note 1)
V
I
< GND
V
O
< GND
V
O
> V
CC
Condition
Units
V
V
V
V
mA
mA
mA
mA
mA
mA
°C
MSL
Moisture Sensitivity
Level 1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. I
O
absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
Supply Voltage
Operating
Data Retention Only
Input Voltage
Output Voltage
(HIGH or LOW State)
(3−State)
HIGH Level Output Current
V
CC
= 3.0 V
−
3.6 V
V
CC
= 2.7 V
−
3.0 V
V
CC
= 2.3 V
−
2.7 V
LOW Level Output Current
V
CC
= 3.0 V
−
3.6 V
V
CC
= 2.7 V
−
3.0 V
V
CC
= 2.3 V
−
2.7 V
Operating Free−Air Temperature
Input Transition Rise or Fall Rate, V
IN
from 0.8 V to 2.0 V, V
CC
= 3.0 V
−55
0
Parameter
Min
2.0
1.5
0
0
0
Typ
2.5, 3.3
2.5, 3.3
Max
3.6
3.6
5.5
V
CC
5.5
−24
−12
−8
+24
+12
+8
+125
10
Units
V
V
I
V
O
V
V
I
OH
mA
I
OL
mA
T
A
Dt/DV
°C
ns/V
ORDERING INFORMATION
Device
MC74LCX573DWG
MC74LCX573DWR2G
MC74LCX573DTG
MC74LCX573DTR2G
NLV74LCX573DTR2G*
Package
SOIC−20
(Pb−Free)
SOIC−20
(Pb−Free)
TSSOP−20
(Pb−Free)
TSSOP−20
(Pb−Free)
TSSOP−20
(Pb−Free)
Shipping
†
38 Units / Rail
1000 Tape & Reel
75 Units / Rail
2500 Tape & Reel
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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3
MC74LCX573
DC ELECTRICAL CHARACTERISTICS
T
A
=
−40°C
to +85°C
Symbol
V
IH
V
IL
V
OH
Characteristic
HIGH Level Input
Voltage (Note 2)
LOW Level Input
Voltage (Note 2)
HIGH Level Out-
put Voltage
Condition
2.3 V
≤
V
CC
≤
2.7 V
2.7 V
≤
V
CC
≤
3.6 V
2.3 V
≤
V
CC
≤
2.7 V
2.7 V
≤
V
CC
≤
3.6 V
2.3 V
≤
V
CC
≤
3.6 V; I
OL
= 100
mA
V
CC
= 2.3 V; I
OH
=
−8
mA
V
CC
= 2.7 V; I
OH
=
−12
mA
V
CC
= 3.0 V; I
OH
=
−18
mA
V
CC
= 3.0 V; I
OH
=
−24
mA
V
OL
LOW Level Out-
put Voltage
2.3 V
≤
V
CC
≤
3.6 V; I
OL
= 100
mA
V
CC
= 2.3 V; I
OL
= 8 mA
V
CC
= 2.7 V; I
OL
= 12 mA
V
CC
= 3.0 V; I
OL
= 16 mA
V
CC
= 3.0 V; I
OL
= 24 mA
I
OZ
I
OFF
I
IN
I
CC
DI
CC
3−State Output
Current
Power Off Leak-
age Current
Input Leakage
Current
Quiescent Supply
Current
Increase in I
CC
per Input
V
CC
= 3.6 V, V
IN
= V
IH
or V
IL
,
V
OUT
= 0 to 5.5 V
V
CC
= 0, V
IN
= 5.5 V or V
OUT
= 5.5 V
V
CC
= 3.6 V, V
IN
= 5.5 V or GND
V
CC
= 3.6 V, V
IN
= 5.5 V or GND
2.3
≤
V
CC
≤
3.6 V; V
IH
= V
CC
−
0.6 V
V
CC
−
0.2
1.8
2.2
2.4
2.2
0.2
0.6
0.4
0.4
0.55
±5
10
±5
10
500
Min
1.7
2.0
0.7
0.8
V
CC
−
0.2
1.8
2.2
2.4
2.2
0.2
0.6
0.4
0.4
0.60
±5
10
±5
10
500
mA
mA
mA
mA
mA
V
Max
T
A
=
−55°C
to +125°C
Min
1.7
2.0
0.7
0.8
V
V
Max
Units
V
2. These values of V
I
are used to test DC electrical characteristics only.
AC CHARACTERISTICS
t
R
= t
F
= 2.5 ns; R
L
= 500
W
Limits
T
A
=
−55°C
to +125°C
V
CC
= 3.3 V
±
0.3 V
C
L
= 50 pF
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
s
t
h
t
w
t
OSHL
t
OSLH
Parameter
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time to HIGH
and LOW Level
Output Disable Time From
High and Low Level
Setup TIme, HIGH or LOW
D
n
to LE
Hold TIme, HIGH or LOW
D
n
to LE
LE Pulse Width, HIGH
Output−to−Output Skew
(Note 3)
Waveform
1
3
2
2
3
3
3
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.3
1.0
1.0
Max
8.0
8.0
8.5
8.5
8.5
8.5
6.5
6.5
V
CC
= 2.7 V
C
L
= 50 pF
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.3
Max
9.0
9.0
9.5
9.5
9.5
9.5
7.0
7.0
V
CC
= 2.5 V
±
0.2 V
C
L
= 30 pF
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
4.0
2.0
4.0
ns
Max
9.6
9.6
10.5
10.5
10.5
10.5
7.8
7.8
Units
ns
ns
ns
ns
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
OSHL
) or LOW−to−HIGH (t
OSLH
); parameter
guaranteed by design.
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4
