Freescale Semiconductor
Data Sheet: Technical Data
Document Number: IMX53AEC
Rev. 7, 05/2015
MCIMX53xA
i.MX53xA Automotive and
Infotainment Applications
Processors
Silicon Version 2.1
Package Information
Plastic Package
Case TEPBGA-2 19 x 19 mm, 0.8 mm pitch
Ordering Information
See
Table 2 on page 4
1
Introduction
1.
The MCIMX53xA (i.MX53xA) automotive
infotainment processor represents Freescale
Semiconductor’s advanced multimedia and
power-efficient implementation of the ARM
Cortex™-A8 core with a high degree of functional
integration, aimed at the growing automotive
infotainment, telematics, HMI, and display-based cluster
markets. This device includes 3D and 2D graphics
processors, 1080i/p video processing, and dual display,
and provides a variety of interfaces. The i.MX53xA
processor features ARM Cortex™-A8 core, which
operates at clock speeds as high as 800 MHz. It provides
DDR2/LVDDR2-800, LPDDR2-800, or DDR3-800
DRAM memories. This device is well suited for graphics
rendering for HMI, navigation, high performance speech
processing with large databases, video processing and
display, audio playback, and many other applications.
The flexibility of the i.MX53xA architecture allows for
its use in a wide variety of applications. As the heart of
the application chipset, the i.MX53xA processor
2.
3.
4.
5.
6.
7.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Functional Part Differences and Ordering
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1. Special Signal Considerations . . . . . . . . . . . . . . . 18
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 18
4.2. Power Supply Requirements and Restrictions . . . 26
4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 29
4.4. Output Buffer Impedance Characteristics . . . . . . 35
4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 39
4.6. System Modules Timing . . . . . . . . . . . . . . . . . . . . 46
4.7. External Peripheral Interfaces Parameters . . . . . 68
4.8. XTAL Electrical Specifications . . . . . . . . . . . . . . 147
Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 148
5.1. Boot Mode Configuration Pins . . . . . . . . . . . . . . 148
5.2. Boot Devices Interfaces Allocation . . . . . . . . . . . 149
5.3. Power Setup During Boot . . . . . . . . . . . . . . . . . . 150
Package Information and Contact Assignments . . . . . 151
6.1. 19x19 mm Package Information . . . . . . . . . . . . . 151
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
© 2011-2015 Freescale Semiconductor, Inc. All rights reserved.
Introduction
provides all the interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, hard drive,
camera sensors, and dual displays.
Features of the i.MX53xA processor include the following:
• Multilevel memory system—The multilevel memory system of the i.MX53xA is based on the L1
instruction and data caches, L2 cache, internal and external memory. The i.MX53xA supports
many types of external memory devices, including DDR2, low voltage DDR2, LPDDR2, DDR3,
NOR Flash, PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed
NAND including eMMC up to rev 4.4.
• Smart speed technology—The i.MX53xA device has power management throughout the IC that
enables the rich suite of multimedia features and peripherals to consume minimum power in both
active and various low power modes. Smart speed technology enables the designer to deliver a
feature-rich product requiring levels of power far lower than industry expectations.
• Multimedia powerhouse—The multimedia performance of the i.MX53xA processor ARM core is
boosted by a multilevel cache system, Neon (including advanced SIMD, 32-bit single-precision
floating point support) and vector floating point coprocessors. The system is further enhanced by
a multi-standard hardware video codec, autonomous image processing unit (IPU), and a
programmable smart DMA (SDMA) controller.
• Powerful graphics acceleration— The i.MX53xA processors provide two independent, integrated
graphics processing units: an OpenGL
®
ES 2.0 3D graphics accelerator (33 Mtri/s, 200 Mpix/s,
and 800 Mpix/s z-plane performance) and an OpenVG™ 1.1 2D graphics accelerator
(200 Mpix/s).
• Interface flexibility—The i.MX53xA processor supports connection to a variety of interfaces,
including LCD controller for two displays and CMOS sensor interface, high-speed USB on-the-go
with PHY, plus three high-speed USB hosts, multiple expansion card ports (high-speed
MMC/SDIO host and others), 10/100 Ethernet controller, and a variety of other popular interfaces
(PATA, UART, I
2
C, and I
2
S serial audio, among others).
• Automotive environment support—Includes interfaces such as two CAN ports, an MLB port, an
ESAI audio interface, and an asynchronous sample rate converter for multichannel/multisource
audio.
• Advanced security—The i.MX53xA processors deliver hardware-enabled security features that
enable secure e-commerce, digital rights management (DRM), information encryption, secure
boot, and secure software downloads. For detailed information about the i.MX53xA security
features contact a Freescale representative.
The i.MX53xA application processor is a follow-on to the i.MX51xA, with improved performance, power
efficiency, and multimedia capabilities.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 7
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Freescale Semiconductor
Introduction
1.1
Functional Part Differences and Ordering Information
Table 1. i.MX53 Parts Functional Differences
Feature
i.MX534
Clusters
800 MHz ARM Cortex™-A8
2 GB, x32 LPDDR2/DDR2/DDR3
no HW acceleration
no HW acceleration
OpenGL/ES 2.0
33 Mtri/s, 200 Mpix/s
i.MX536
Video and Navigation
ARM 800 MHz Cortex™-A8
2 GB, x32 LPDDR2/DDR2/DDR3
Hardware (1080p30)
Hardware (720p30)
OpenGL/ES 2.0
33 Mtri/s, 200 Mpix/s
OpenVG 1.1, 200 Mpix/s
Parallel, LVDS
VGA HD1080p60
2x 20-bit Parallel
10/100, IEEE1588
S-ATA II 1.5 Gbps
2 x FlexCAN
MLB50
Four HS USB2.0:
1xHS OTG + PHY
1xHost + PHY
2xHost + ULPI/IC-USB
3x SD/MMC 4.3
1x SD/MMC 4.4
3x SPI
3x I2C
5x UART, P-ATA, 3x I2S, S/PDIF Tx/Rx, ESAI
19x19 0.8P TE-BGA
Automotive AEC-Q100
Table 1shows
the functional differences between the different parts in the i.MX53 family.
Example Applications
Core
Memory
Video Decode
Video Encode
3D GPU
2D GPU
LCD IF
Video Out
Camera I/F
Ethernet
SATA
CAN
MLB
USB
OpenVG 1.1, 200 Mpix/s
Parallel, LVDS
VGA HD1080p60
2x 20-bit Parallel
10/100, IEEE1588
S-ATA II 1.5 Gbps
2 x FlexCAN
MLB50
Four HS USB2.0:
1xHS OTG + PHY
1xHost + PHY
2xHost + ULPI/IC-USB
3x SD/MMC 4.3
1x SD/MMC 4.4
3x SPI
3x I2C
5x UART, P-ATA, 3x I2S, S/PDIF Tx/Rx, ESAI
19x19 0.8P TE-BGA
Automotive AEC-Q100
SDIO I/F
SPI I/F
I2C I/F
Other
Package
Qual.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 7
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Introduction
Table 2
provides ordering information.
Table 2. Ordering Information
Part Number
MCIMX536AVV8C
MCIMX534AVV8C
1
Mask Set
3N78C
3N78C
CPU Frequency
800 MHz
800 MHz
Notes
—
—
Package
1
19 x 19 mm, 0.8 mm pitch BGA
Case TEPBGA-2
19 x 19 mm, 0.8 mm pitch BGA
Case TEPBGA-2
Case TEPBGA-2 is RoHS compliant, lead-free MSL (moisture sensitivity level) 3.
1.2
Features
The i.MX53xA multimedia applications processor (AP) is based on the ARM Platform, which has the
following features:
• MMU, L1 instruction and L1 data cache
• Unified L2 cache
• Maximum frequency of the core (including Neon, VFPv3 and L1 cache): 800 MHz
• Neon coprocessor (SIMD media processing architecture) and vector floating point (VFP-Lite)
coprocessor supporting VFPv3
• TrustZone
The memory system consists of the following components:
• Level 1 cache:
— Instruction (32 Kbyte)
— Data (32 Kbyte)
• Level 2 cache:
— Unified instruction and data (256 Kbyte)
• Level 2 (internal) memory:
— Boot ROM, including HAB (64 Kbyte)
— Internal multimedia/shared, fast access RAM (128 Kbyte)
— Secure/non-secure RAM (16 Kbyte)
• External memory interfaces:
— 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte
— 32-bit LPDDR2
— 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC
— 8/16-bit NOR Flash, PSRAM, and cellular RAM.
— 32-bit multiplexed mode NOR Flash, PSRAM & cellular RAM.
— 8-bit Asynchronous (DTACK mode) EIM interface.
— All EIM pins are muxed on other interfaces (data with NFC pins). I/O muxing logic selects
EIM port, as primary muxing at system boot.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 7
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Freescale Semiconductor
Introduction
— Samsung OneNAND™ and managed NAND including eMMC up to rev 4.4 (in muxed I/O
mode)
The i.MX53xA system is built around the following system on chip interfaces:
• 64-bit AMBA AXI v1.0 bus—used by ARM platform, multimedia accelerators (such as VPU, IPU,
GPU3D, GPU2D) and the external memory controller (EXTMC) operating at 200 MHz.
• 32-bit AMBA AHB 2.0 bus—used by the rest of the bus master peripherals operating at 133 MHz.
• 32-bit IP bus—peripheral bus used for control (and slow data traffic) of the most system peripheral
devices operating at 66 MHz.
The i.MX53xA makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia
performance. The use of hardware accelerators provides both high performance and low power
consumption while freeing up the CPU core for other tasks.
The i.MX53xA incorporates the following hardware accelerators:
• VPU, version 3—video processing unit
• GPU3D—3D graphics processing unit, OpenGL ES 2.0, version 3, 33 Mtri/s, 200 Mpix/s, and
800 Mpix/s z-plane performance, 256 Kbyte RAM memory
• GPU2D—2D graphics accelerator, OpenVG 1.1, version 1, 200 Mpix/s performance,
• IPU, version 3M—image processing unit
• ASRC—asynchronous sample rate converter
The i.MX53xA includes the following interfaces to external devices:
NOTE
Not all interfaces are available simultaneously, depending on I/O
multiplexer configuration.
•
Hard disk drives:
— PATA, up to U-DMA mode 5, 100 MB/s
— SATA II, 1.5 Gbps
Displays:
— Five interfaces available. Total rate of all interfaces is up to 180 Mpixels/s, 24 bpp. Up to two
interfaces may be active at once.
— Two parallel 24-bit display ports. The primary port is up to 165 Mpix/s (for example,
UXGA at 60 Hz).
— LVDS serial ports: one dual channel port up to 165 Mpix/s or two independent single channel
ports up to 85 MP/s (for example, WXGA at 60 Hz) each.
— TV-out/VGA port up to 150 Mpix/s (for example, 1080p60).
Camera sensors:
— Two parallel 20-bit camera ports. Primary up to 180-MHz peak clock frequency, secondary up
to 120-MHz peak clock frequency.
Expansion cards:
•
•
•
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 7
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