MCP3204/3208
2.7V 4-Channel/8-Channel 12-Bit A/D Converters
with SPI
®
Serial Interface
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
12-bit resolution
± 1 LSB max DNL
± 1 LSB max INL (MCP3204/3208-B)
± 2 LSB max INL (MCP3204/3208-C)
4 (MCP3204) or 8 (MCP3208) input channels
Analog inputs programmable as single-ended or
pseudo differential pairs
On-chip sample and hold
SPI
®
serial interface (modes 0,0 and 1,1)
Single supply operation: 2.7V - 5.5V
100ksps max. sampling rate at V
DD
= 5V
50ksps max. sampling rate at V
DD
= 2.7V
Low power CMOS technology
- 500 nA typical standby current, 2µA max.
- 400 µA max. active current at 5V
Industrial temp range: -40°C to +85°C
Available in PDIP, SOIC and TSSOP packages
PACKAGE TYPES
PDIP, SOIC, TSSOP
CH0
CH1
CH2
CH3
NC
NC
DGND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
V
REF
AGND
CLK
D
OUT
D
IN
CS/SHDN
MCP3204
PDIP, SOIC
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
V
REF
AGND
CLK
D
OUT
D
IN
CS/SHDN
DGND
MCP3208
•
•
APPLICATIONS
•
•
•
•
Sensor Interface
Process Control
Data Acquisition
Battery Operated Systems
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
REF
CH0
CH1
V
SS
DESCRIPTION
The Microchip Technology Inc. MCP3204/3208
devices are successive approximation 12-bit Ana-
log-to-Digital (A/D) Converters with on-board sample
and hold circuitry. The MCP3204 is programmable to
provide two pseudo-differential input pairs or four sin-
gle-ended inputs. The MCP3208 is programmable to
provide four pseudo-differential input pairs or eight sin-
gle-ended inputs. Differential Nonlinearity (DNL) is
specified at ±1 LSB, and Integral Nonlinearity (INL) is
offered in ±1 LSB (MCP3204/3208-B) and ±2 LSB
(MCP3204/3208-C) versions. Communication with the
devices is done using a simple serial interface compat-
ible with the SPI protocol. The devices are capable of
conversion rates of up to 100ksps. The MCP3204/3208
devices operate over a broad voltage range (2.7V -
5.5V). Low current design permits operation with typi-
cal standby and active currents of only 500nA and
320µA, respectively. The MCP3204 is offered in 14-pin
PDIP, 150mil SOIC and TSSOP packages, and the
MCP3208 is offered in 16-pin PDIP and SOIC pack-
ages.
Input
Channel
Mux
DAC
Comparator
CH7*
Sample
and
Hold
Control Logic
12-Bit SAR
Shift
Register
CS/SHDN D
IN
CLK
D
OUT
*Note: Channels 5-7 available on MCP3208 Only
©
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 1
MCP3204/3208
1.0
1.1
ELECTRICAL
CHARACTERISTICS
Maximum Ratings*
PIN FUNCTION TABLE
NAME
V
DD
DGND
AGND
CH0-CH7
CLK
D
IN
D
OUT
CS/SHDN
V
REF
FUNCTION
+2.7V to 5.5V Power Supply
Digital Ground
Analog Ground
Analog Inputs
Serial Clock
Serial Data In
Serial Data Out
Chip Select/Shutdown Input
Reference Voltage Input
V
DD
.........................................................................7.0V
All inputs and outputs w.r.t. V
SS
...... -0.6V to V
DD
+0.6V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied......-65°C to +125°C
Soldering temperature of leads (10 seconds) .. +300°C
ESD protection on all pins ...................................> 4kV
*Notice: Stresses above those listed under “Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
ELECTRICAL CHARACTERISTICS
All parameters apply at V
DD
= 5V, V
SS
= 0V, V
REF
= 5V, T
AMB
= -40°C to +85°C, f
SAMPLE
= 100ksps and
f
CLK
= 20*f
SAMPLE
, unless otherwise noted.
PARAMETER
Conversion Rate
Conversion Time
Analog Input Sample Time
Throughput Rate
DC Accuracy
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Dynamic Performance
Total Harmonic Distortion
Signal to Noise and Distortion
(SINAD)
Spurious Free Dynamic
Range
Reference Input
Voltage Range
Current Drain
Analog Inputs
Input Voltage Range for
CH0-CH7 in Single-Ended
Mode
Input Voltage Range for IN+ In
pseudo-differential Mode
Input Voltage Range for IN- In
pseudo-differential Mode
Leakage Current
V
SS
IN-
V
SS
-100
0.001
V
REF
V
REF
+IN-
V
SS
+100
±1
mV
µA
V
0.25
100
0.001
V
DD
150
3
V
µA
µA
Note 2
CS = V
DD
= 5V
-82
72
86
dB
dB
dB
V
IN
= 0.1V to 4.9V@1kHz
V
IN
= 0.1V to 4.9V@1kHz
V
IN
= 0.1V to 4.9V@1kHz
INL
DNL
12
±0.75
±1
±0.5
±1.25
±1.25
±1
±2
±1
±3
±5
bits
LSB
LSB
LSB
LSB
MCP3204/3208-B
MCP3204/3208-C
No missing codes over
temperature
t
CONV
t
S
AMPLE
f
SAMPLE
1.5
100
50
12
clock
cycles
clock
cycles
ksps
ksps
V
DD
= V
REF
= 5V
V
DD
= V
REF
= 2.7V
SYMBOL
MIN.
TYP.
MAX.
UNITS
CONDITIONS
DS21298B-page 2
Preliminary
©
1999 Microchip Technology Inc.
MCP3204/3208
ELECTRICAL CHARACTERISTICS (CONTINUED)
All parameters apply at V
DD
= 5V, V
SS
= 0V, V
REF
= 5V, T
AMB
= -40°C to +85°C, f
SAMPLE
= 100ksps and
f
CLK
= 20*f
SAMPLE
, unless otherwise noted.
PARAMETER
Analog Inputs (Continued)
Switch Resistance
Sample Capacitor
Digital Input/Output
Data Coding Format
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Leakage Current
Pin Capacitance
(All Inputs/Outputs)
Timing Parameters
Clock Frequency
Clock High Time
Clock Low Time
CS Fall To First Rising CLK
Edge
Data Input Setup Time
Data Input Hold Time
CLK Fall To Output Data Valid
CLK Fall To Output Enable
CS Rise To Output Disable
CS Disable Time
D
OUT
Rise Time
D
OUT
Fall Time
Power Requirements
Operating Voltage
Operating Current
Standby Current
V
DD
I
DD
I
DDS
2.7
320
225
0.5
5.5
400
2
V
µA
µA
V
DD
= V
REF
= 5V, D
OUT
unloaded
V
DD
= V
REF
= 2.7V, D
OUT
unloaded
CS = V
DD
= 5.0V
f
CLK
t
HI
t
LO
t
SUCS
t
SU
t
HD
t
DO
t
EN
t
DIS
t
CSH
t
R
t
F
500
100
100
250
250
100
50
50
200
200
100
2.0
1.0
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Test Circuits, Figure 1-2
(Note 1)
See Test Circuits, Figure 1-2
(Note 1)
See Test Circuits, Figure 1-2
See Test Circuits, Figure 1-2
See Test Circuits, Figure 1-2
V
DD
= 5V (Note 3)
V
DD
= 2.7V (Note 3)
V
IH
V
IL
V
OH
V
OL
I
LI
I
LO
C
IN
, C
OUT
-10
-10
4.1
0.4
10
10
10
Straight Binary
0.7 V
DD
0.3 V
DD
V
V
V
V
µA
µA
pF
I
OH
= -1mA, V
DD
= 4.5V
I
OL
= 1mA, V
DD
= 4.5V
V
IN
= V
SS
or V
DD
V
OUT
= V
SS
or V
DD
V
DD
= 5.0V (Note 1)
T
AMB
= 25°C, f = 1 MHz
1K
20
Ω
pF
See Figure 4-1
See Figure 4-1
SYMBOL
MIN.
TYP.
MAX.
UNITS
CONDITIONS
Note 1:
This parameter is guaranteed by characterization and not 100% tested.
Note 2:
See graphs that relate linearity performance to V
REF
levels.
Note 3:
Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity
performance, especially at elevated temperatures. See Section 6.2 for more information.
©
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 3
MCP3204/3208
t
CSH
CS
t
SUCS
t
HI
CLK
t
SU
D
IN
t
HD
t
LO
MSB IN
t
EN
t
DO
NULL BIT
MSB OUT
t
R
t
F
t
DIS
LSB
D
OUT
FIGURE 1-1:
Serial Interface Timing.
Load circuit for t
R
, t
F
,
t
DO
1.4V
Load circuit for t
DIS
and t
EN
Test Point
V
DD
t
DIS
Waveform 2
V
DD
/2
3K
D
OUT
Test Point
D
OUT
3K
100pF
t
EN
Waveform
t
DIS
Waveform 1
C
L
= 100pF
V
SS
Voltage Waveforms for t
R
, t
F
Voltage Waveforms for t
EN
D
OUT
V
OH
V
OL
CS
1
CLK
D
OUT
2
3
4
B11
t
R
t
F
t
EN
Voltage Waveforms for t
DO
Voltage Waveforms for t
DIS
CS
CLK
D
OUT
Waveform 1*
V
IH
90%
t
DO
D
OUT
T
DIS
D
OUT
Waveform 2†
* Waveform 1 is for an output with internal condi-
tions such that the output is high, unless dis-
abled by the output control.
† Waveform 2 is for an output with internal condi-
tions such that the output is low, unless disabled
by the output control.
10%
FIGURE 1-2:
Test Circuits.
DS21298B-page 4
Preliminary
©
1999 Microchip Technology Inc.
MCP3204/3208
2.0
TYPICAL PERFORMANCE CHARACTERISTICS
Note:
Unless otherwise indicated, V
DD
= V
REF
= 5V, V
SS
= 0V, f
SAMPLE
= 100ksps, f
CLK
= 20* f
SAMPLE
,T
A
= 25°C
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
25
50
75
100
125
150
Negative INL
Positive INL
2.0
1.5
1.0
V
DD
= V
REF
= 2.7V
INL (LSB)
INL (LSB)
Positive INL
0.5
0.0
-0.5
-1.0
-1.5
-2.0
0
10
20
30
40
50
60
70
80
Negative INL
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-1:
Rate.
Integral Nonlinearity (INL) vs. Sample
FIGURE 2-4:
Integral Nonlinearity (INL) vs. Sample
Rate (V
DD
= 2.7V).
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
0
1
2.0
1.5
1.0
Positive INL
Positive INL
INL(LSB)
INL(LSB)
0.5
0.0
-0.5
-1.0
-1.5
-2.0
Negative INL
Negative INL
2
3
4
5
6
0.0
0.5
1.0
1.5
2.0
2.5
3.0
V
REF
(V)
V
REF
(V)
FIGURE 2-2:
Integral Nonlinearity (INL) vs. V
REF
.
FIGURE 2-5:
(V
DD
= 2.7V).
Integral Nonlinearity (INL) vs. V
REF
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512
1024
1536
2048 2560
3072 3584
4096
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512
1024 1536
2048
2560
3072 3584
4096
V
DD
= V
REF
= 2.7V
F
SAMPLE
= 50ksps
INL (LSB)
Digital Code
INL (LSB)
Digital Code
FIGURE 2-3:
Integral Nonlinearity (INL) vs. Code
(Representative Part).
FIGURE 2-6:
Integral Nonlinearity (INL) vs. Code
(Representative Part, V
DD
= 2.7V).
©
1999 Microchip Technology Inc.
Preliminary
DS21298B-page 5
