MD56V62160-12TA,MD56V62160-12TA pdf中文资料,MD56V62160-12TA引脚图,MD56V62160-12TA电路-Datasheet-电子工程世界

器件参数

参数名称

属性值

是否Rohs认证

不符合

厂商名称

LAPIS Semiconductor Co Ltd

零件包装代码

TSOP2

包装说明

TSOP2, TSOP54,.46,32

针数

Reach Compliance Code

unknown

ECCN代码

EAR99

访问模式

FOUR BANK PAGE BURST

最长访问时间

10 ns

其他特性

AUTO/SELF REFRESH

最大时钟频率 (fCLK)

83 MHz

I/O 类型

COMMON

交错的突发长度

2,4,8

JESD-30 代码

R-PDSO-G54

JESD-609代码

长度

22.22 mm

内存密度

67108864 bit

内存集成电路类型

SYNCHRONOUS DRAM

内存宽度

功能数量

端口数量

端子数量

字数

4194304 words

字数代码

4000000

工作模式

SYNCHRONOUS

最高工作温度

70 °C

最低工作温度

组织

4MX16

输出特性

3-STATE

封装主体材料

PLASTIC/EPOXY

封装代码

TSOP2

封装等效代码

TSOP54,.46,32

封装形状

RECTANGULAR

封装形式

SMALL OUTLINE, THIN PROFILE

峰值回流温度（摄氏度）

NOT SPECIFIED

电源

3.3 V

认证状态

Not Qualified

刷新周期

4096

座面最大高度

1.2 mm

自我刷新

YES

连续突发长度

2,4,8

最大待机电流

0.002 A

最大压摆率

0.18 mA

最大供电电压 (Vsup)

3.6 V

最小供电电压 (Vsup)

3 V

标称供电电压 (Vsup)

3.3 V

表面贴装

YES

技术

CMOS

温度等级

COMMERCIAL

端子面层

Tin/Lead (Sn/Pb)

端子形式

GULL WING

端子节距

0.8 mm

端子位置

DUAL

处于峰值回流温度下的最长时间

NOT SPECIFIED

宽度

10.16 mm

文档预览

Dear customers,

About the change in the name such as "Oki Electric Industry Co. Ltd." and

"OKI" in documents to OKI Semiconductor Co., Ltd.

The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI

Semiconductor Co., Ltd. on October 1, 2008.

Therefore, please accept that although

the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"

remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".

It is a change of the company name, the company trademark, and the logo, etc. , and

NOT a content change in documents.

October 1, 2008

OKI Semiconductor Co., Ltd.

550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan

http://www.okisemi.com/en/

E2G1052-17-X1

¡ Semiconductor

MD56V62160/H

¡ Semiconductor

This version: Mar. 1998

MD56V62160/H

4-Bank

1,048,576-Word

16-Bit SYNCHRONOUS DYNAMIC RAM

DESCRIPTION

The MD56V62160/H is a 4-bank

1,048,576-word

16-bit synchronous dynamic RAM,

fabricated in Oki's CMOS silicon-gate process technology. The device operates at 3.3 V. The inputs

and outputs are LVTTL compatible.

FEATURES

•

Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell

4-bank

1,048,576-word

16-bit configuration

3.3 V power supply,

±0.3

V tolerance

Input

: LVTTL compatible

Output : LVTTL compatible

Refresh : 4096 cycles/64 ms

Programmable data transfer mode

–

CAS

latency (2, 3)

– Burst length (2, 4, 8)

– Data scramble (sequential, interleave)

• CBR auto-refresh, Self-refresh capability

• Package:

54-pin 400 mil plastic TSOP (Type II) (TSOPII54-P-400-0.80-K) (Product : MD56V62160/H-xxTA)

xx indicates speed rank.

PRODUCT FAMILY

Family

MD56V62160-10

MD56V62160-12

MD56V62160H-15

Max.

Frequency

100 MHz

83 MHz

66 MHz

Access Time (Max.)

AC2

9 ns

14 ns

9 ns

AC3

9 ns

10 ns

9 ns

1/28

¡ Semiconductor

PIN CONFIGURATION (TOP VIEW)

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

LDQM

CAS

RAS

A13/BA0

A12/BA1

A10

MD56V62160/H

DQ16

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

UDQM

CLK

CKE

A11

54-Pin Plastic TSOP (II)

(K Type)

Pin Name

CLK

CKE

A0 - A11

A12, A13

RAS

CAS

Function

System Clock

Chip Select

Clock Enable

Address

Bank Select Address

Row Address Strobe

Column Address Strobe

Write Enable

Pin Name

DQi

Function

Data Input/Output

Power Supply (3.3 V)

Ground (0 V)

Data Output Power Supply (3.3 V)

Data Output Ground (0 V)

No Connection

UDQM, LDQM Data Input/Output Mask

Note:

The same power supply voltage must be provided to every V

pin and V

Q pin.

The same GND voltage level must be provided to every V

pin and V

Q pin.

2/28

¡ Semiconductor

MD56V62160/H

PIN DESCRIPTION

CLK

CKE

Fetches all inputs at the "H" edge.

Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,

UDQM and LDQM.

Masks system clock to deactivate the subsequent CLK operation.

If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is

deactivated. CKE should be asserted at least one cycle prior to a new command.

Address

Row & column multiplexed.

Row address: RA0 – RA11

Column address: CA0 – CA7

A12, A13

(BA1, BA0)

RAS

CAS

UDQM,

LDQM

Masks the read data of two clocks later when UDQM and LDQM are set "H" at the "H" edge of the clock signal.

Masks the write data of the same clock when UDQM and LDQM are set "H" at the "H" edge of the clock signal.

UDQM controls upper byte and LDQM controls lower byte.

DQi

Data inputs/outputs are multiplexed on the same pin.

Functionality depends on the combination. For details, see the function truth table.

Bank Access pins. These pins are dedicated to select one of 4 banks.

3/28

¡ Semiconductor

BLOCK DIAGRAM

MD56V62160/H

CLK

CKE

CLOCK

BUFFER

Command

Decoding

Logic

Command

Buffers

Control

Logic

A0 -

A13

Address

Buffers

Mode

Latency

& Burst

controller

Column

Address

Latches

& Counter

Column Decoders

Sense Amplifiers

RAS

CAS

UDQM

LDQM

Row

Address

Latches

& Refresh

Counter

Row Decoders

Word Drivers

Memory

Cells

BANK A

BANK B

BANK C

BANK D

Input

Buffers

Input

Data

DQ1 - DQ16

Output

Data

Output

Buffers

4/28

参数对比

与MD56V62160-12TA相近的元器件有：MD56V62160-10TA、MD56V62160H-15TA。描述及对比如下：

型号	MD56V62160-12TA	MD56V62160-10TA	MD56V62160H-15TA
描述	Synchronous DRAM, 4MX16, 10ns, CMOS, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54	Synchronous DRAM, 4MX16, 9ns, CMOS, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54	Synchronous DRAM, 4MX16, 9ns, CMOS, PDSO54, 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP2-54
是否Rohs认证	不符合	不符合	不符合
零件包装代码	TSOP2	TSOP2	TSOP2
包装说明	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32
针数	54	54	54
Reach Compliance Code	unknown	unknown	unknown
ECCN代码	EAR99	EAR99	EAR99
访问模式	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
最长访问时间	10 ns	9 ns	9 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	83 MHz	100 MHz	66 MHz
I/O 类型	COMMON	COMMON	COMMON
交错的突发长度	2,4,8	2,4,8	2,4,8
JESD-30 代码	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54
JESD-609代码	e0	e0	e0
长度	22.22 mm	22.22 mm	22.22 mm
内存密度	67108864 bit	67108864 bit	67108864 bit
内存集成电路类型	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
内存宽度	16	16	16
功能数量	1	1	1
端口数量	1	1	1
端子数量	54	54	54
字数	4194304 words	4194304 words	4194304 words
字数代码	4000000	4000000	4000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C
组织	4MX16	4MX16	4MX16
输出特性	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSOP2	TSOP2	TSOP2
封装等效代码	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
电源	3.3 V	3.3 V	3.3 V
认证状态	Not Qualified	Not Qualified	Not Qualified
刷新周期	4096	4096	4096
座面最大高度	1.2 mm	1.2 mm	1.2 mm
自我刷新	YES	YES	YES
连续突发长度	2,4,8	2,4,8	2,4,8
最大待机电流	0.002 A	0.002 A	0.002 A
最大压摆率	0.18 mA	0.21 mA	0.16 mA
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	3 V	3 V	3 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES
技术	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	GULL WING	GULL WING	GULL WING
端子节距	0.8 mm	0.8 mm	0.8 mm
端子位置	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	10.16 mm	10.16 mm	10.16 mm
厂商名称	LAPIS Semiconductor Co Ltd	-	LAPIS Semiconductor Co Ltd