Dear customers,
About the change in the name such as "Oki Electric Industry Co. Ltd." and
"OKI" in documents to OKI Semiconductor Co., Ltd.
The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI
Semiconductor Co., Ltd. on October 1, 2008.
Therefore, please accept that although
the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"
remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".
It is a change of the company name, the company trademark, and the logo, etc. , and
NOT a content change in documents.
October 1, 2008
OKI Semiconductor Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan
http://www.okisemi.com/en/
OKI Semiconductor
MD56V62162J
4-Bank
×
1,048,576-Word
×
16-Bit SYNCHRONOUS DYNAMIC RAM
FEDD56V62162J-01
Issue Date: Jan. 30, 2007
DESCRIPTION
The MD56V62162J is a 4-Bank
×
1,048,576-word
×
16-bit Synchronous dynamic. The device operates
at 3.3 V. The inputs and outputs are LVTTL compatible.
FEATURES
•
Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell
• 4-Bank
×
1,048,576-word
×
16-bit configuration
•
Single 3.3 V power supply,
±0.3
V tolerance
•
Input : LVTTL compatible
•
Output : LVTTL compatible
•
Refresh : 4096 cycles/64 ms
•
Programmable data transfer mode
-
CAS
Latency (2, 3)
- Burst Length (1, 2, 4, 8, Full Page)
- Data scramble (sequential, interleave)
• A
uto-refresh, Self-refresh capability
• Packages:
54-pin 400 mil plastic TSOP (TypeII)
(
TSOP(2)54-P-400-0.80-K
)
(Product: MD56V62162J-xxTA)
xx indicates speed rank.
PRODUCT FAMILY
Family
Max.
Frequency
143 MHz
133 MHz
125 MHz
100 MHz
Access Time (Max.)
t
AC2
5.4 ns
5.4 ns
6 ns
6 ns
t
AC3
5.4 ns
5.4 ns
6 ns
6 ns
MD56V62162J-7
MD56V62162J-75
MD56V62162J-8
MD56V62162J-10
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FEDD56V62162J-01
OKI Semiconductor
MD56V62162J
PIN CONFIGURATION (TOP VIEW)
V
CC
1
DQ1 2
V
CC
Q 3
DQ2 4
DQ3 5
V
SS
Q 6
DQ4 7
DQ5 8
V
CC
Q 9
DQ6 10
DQ7 11
V
SS
Q 12
DQ8 13
V
CC
14
LDQM 15
WE
16
CAS
17
RAS
18
CS
19
A13 20
A12 21
A10 22
A0 23
A1 24
A2 25
A3 26
V
CC
27
54 V
SS
53 DQ16
52 V
SS
Q
51 DQ15
50 DQ14
49 V
CC
Q
48 DQ13
47 DQ12
46 V
SS
Q
45 DQ11
44 DQ10
43 V
CC
Q
42 DQ9
41 V
SS
40 NC
39 UDQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 V
SS
54-Pin Plastic TSOP(II)
(K Type)
Pin Name
CLK
CS
CKE
A0–A11
A12, A13
RAS
CAS
WE
Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Pin Name
UDQM, LDQM
DQi
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Function
Data Input/ Output Mask
Data Input/ Output
Power Supply (3.3 V)
Ground (0 V)
Data Output Power Supply (3.3 V)
Data Output Ground (0 V)
No Connection
Note : The same power supply voltage must be provided to every V
CC
pin and V
CC
Q pin.
The same GND voltage level must be provided to every V
SS
pin and V
SS
Q pin.
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FEDD56V62162J-01
OKI Semiconductor
MD56V62162J
PIN DESCRIPTION
CLK
CS
Fetches all inputs at the “H” edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
UDQM and LDQM.
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Row address
: RA0 – RA11
Column Address
: CA0 – CA7
Slects bank to be activated during row address latch time and selects bank for precharge and
read/write during column address latch time.
CKE
Address
A13, A12
(BA0, BA1)
RAS
CAS
WE
UDQM,
LDQM
DQi
Functionality depends on the combination. For details, see the function truth table.
Masks the read data of two clocks later when UDQM and LDQM are set “H” at the “H” edge of the
clock signal. Masks the write data of the same clock when UDQM and LDQM are set “H” at the “H”
edge of the clock signal. UDQM controls upper byte and LDQM controls lower byte.
Data inputs/outputs are multiplexed on the same pin.
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FEDD56V62162J-01
OKI Semiconductor
MD56V62162J
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Voltage on Any Pin Relative to V
SS
V
CC
Supply Voltage
Storage Temperature
Power Dissipation
Short Circuit Output Current
Operating Temperature
Symbol
V
IN
, V
OUT
V
CC
, V
CC
Q
T
stg
P
D*
I
OS
T
opr
Value
–0.5 to V
CC
+ 0.5
–0.5 to 4.6
–55 to 150
1000
50
0 to 70
Unit
V
V
°C
mW
mA
°C
*: Ta = 25°C
Recommended Operating Conditions
(Voltages referenced to V
SS
= V
SS
Q = 0 V)
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
, V
CC
Q
V
IH
V
IL
Min.
3.0
2.0
−0.3
(*2)
Typ.
3.3
⎯
⎯
Max.
3.6
V
CC
+ 0.3
(*1)
0.8
Unit
V
V
V
Notes: *1. The input voltage is V
CC
+ 2.0V when the pulse width is less than 10ns (the pulse width is with respect
to the point at which V
CC
is applied).
*2. The input voltage is V
SS
−
2.0V when the pulse width is less than 10ns (the pulse width respect to the
point at which V
SS
is applied).
Pin Capacitance
(V
bias
= 1.4 V, Ta = 25°C, f = 1 MHz)
Parameter
Input Capacitance (CLK)
Input Capacitance
(RAS,
CAS, WE, CS,
CKE, UDQM, LDQM,
A0 - A13)
Input/Output Capacitance (DQ1 – DQ16)
C
OUT
⎯
6.5
pF
C
IN
⎯
5
pF
Symbol
C
CLK
Min.
⎯
Max.
4
Unit
pF
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