Dear customers,
About the change in the name such as "Oki Electric Industry Co. Ltd." and
"OKI" in documents to OKI Semiconductor Co., Ltd.
The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI
Semiconductor Co., Ltd. on October 1, 2008.
Therefore, please accept that although
the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"
remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".
It is a change of the company name, the company trademark, and the logo, etc. , and
NOT a content change in documents.
October 1, 2008
OKI Semiconductor Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan
http://www.okisemi.com/en/
E2G1051-17-X1
¡ Semiconductor
MD56V62800/H
¡ Semiconductor
This version: Mar. 1998
MD56V62800/H
Pr
el
im
in
ar
y
4-Bank
¥
2,097,152-Word
¥
8-Bit SYNCHRONOUS DYNAMIC RAM
DESCRIPTION
The MD56V62800/H is a 4-bank
¥
2,097,152-word
¥
8-bit synchronous dynamic RAM, fabricated
in Oki's CMOS silicon-gate process technology. The device operates at 3.3 V. The inputs and
outputs are LVTTL compatible.
FEATURES
•
•
•
•
•
•
•
Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell
4-bank
¥
2,097,152-word
¥
8-bit configuration
3.3 V power supply,
±0.3
V tolerance
Input
: LVTTL compatible
Output : LVTTL compatible
Refresh : 4096 cycles/64 ms
Programmable data transfer mode
–
CAS
latency (2, 3)
– Burst length (2, 4, 8)
– Data scramble (sequential, interleave)
• CBR auto-refresh, Self-refresh capability
• Package:
54-pin 400 mil plastic TSOP (Type II) (TSOPII54-P-400-0.80-K) (Product : MD56V62800/H-xxTA)
xx indicates speed rank.
PRODUCT FAMILY
Family
MD56V62800-10
MD56V62800-12
MD56V62800H-15
Max.
Frequency
100 MHz
83 MHz
66 MHz
Access Time (Max.)
t
AC2
9 ns
14 ns
9 ns
t
AC3
9 ns
10 ns
9 ns
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¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
V
CC
DQ1
V
CC
Q
NC
DQ2
V
SS
Q
NC
DQ3
V
CC
Q
NC
DQ4
V
SS
Q
NC
V
CC
NC
WE
CAS
RAS
CS
A13/BA0
A12/BA1
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
MD56V62800/H
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
V
SS
53
DQ8
52
V
SS
Q
51
NC
50
DQ7
49
V
CC
Q
48
NC
47
DQ6
46
V
SS
Q
45
NC
44
DQ5
43
V
CC
Q
42
NC
41
V
SS
40
NC
39
DQM
38
CLK
37
CKE
36
NC
35
A11
34
A9
33
A8
32
A7
31
A6
30
A5
29
A4
28
V
SS
54-Pin Plastic TSOP (II)
(K Type)
Pin Name
CLK
CS
CKE
A0 - A11
A12, A13
RAS
CAS
WE
Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Pin Name
DQM
DQi
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Function
Data Input/Output Mask
Data Input/Output
Power Supply (3.3 V)
Ground (0 V)
Data Output Power Supply (3.3 V)
Data Output Ground (0 V)
No Connection
Note:
The same power supply voltage must be provided to every V
CC
pin and V
CC
Q pin.
The same GND voltage level must be provided to every V
SS
pin and V
SS
Q pin.
2/28
¡ Semiconductor
MD56V62800/H
PIN DESCRIPTION
CLK
CS
CKE
Fetches all inputs at the "H" edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE and DQM.
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Address
Row & column multiplexed.
Row address: RA0 – RA11
Column address: CA0 – CA8
A12, A13
(BA1, BA0)
RAS
CAS
WE
DQM
DQi
Masks the read data of two clocks later when DQM is set "H" at the "H" edge of the clock signal.
Masks the write data of the same clock when DQM is set "H" at the "H" edge of the clock signal.
Data inputs/outputs are multiplexed on the same pin.
Functionality depends on the combination. For details, see the function truth table.
Bank Access pins. These pins are dedicated to select one of 4 banks.
3/28
¡ Semiconductor
BLOCK DIAGRAM
MD56V62800/H
CLK
CKE
CLOCK
BUFFER
Command
Decoding
Logic
Command
Buffers
Control
Logic
A0 -
A13
Address
Buffers
Mode
Register
Latency
& Burst
controller
Column
Address
Latches
& Counter
Column Decoders
Sense Amplifiers
CS
RAS
CAS
WE
DQM
Row
Address
Latches
& Refresh
Counter
Row Decoders
Word Drivers
Memory
Cells
BANK A
BANK B
BANK C
BANK D
Input
Buffers
Input
Data
Register
DQ1 - DQ8
Output
Data
Register
Output
Buffers
4/28
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