®
ST-BUS™ FAMILY
MH89760B
T1/ESF Framer & Interface
Preliminary Information
Features
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•
•
•
•
•
•
•
•
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Complete interface to a bidirectional T1 link
D3/D4 or ESF framing and SLC-96 compatible
Two frame elastic buffer with 32µs jitter buffer
Insertion and detection of A, B, C, D bits
Signalling freeze, optional debounce
Selectable B8ZS, jammed bit (ZCS) or no zero
code suppression
Yellow and blue alarm signal capabilities
Bipolar violation count, F
T
error count, CRC
error count
Frame and superframe sync. signals, Tx and Rx
Per channel, overall, and remote loop around
8 kHz synchronization output
Digital phase detector between T1 line and ST-
BUS
ST-BUS compatible
Pin compatible with the MH89760
Inductorless clock recovery
Loss of Signal (LOS) indication
Available in standard, narrow and surface
mount formats
MH89760B
MH89760BN
MH89760BS
ISSUE 5
May 1995
Ordering Information
40 Pin DIL Hybrid 1.3" row pitch
40 Pin DIL Hybrid 0.8" row pitch
40 Pin Surface Mount Hybrid
0°C to 70°C
Description
The MH89760B is a complete T1 interface solution,
meeting the Extended Super Frame (ESF), D3/D4
and SLC-96 formats. The MH89760B interfaces to
the DS11.544 Mbit/sec digital trunk.
The MH89760B is a pin-compatible enhancement of
the MH89760, permitting the removal of the tuneable
inductor and inclusion of the external NAND gate
used for generating RxD.
Applications
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•
•
DS1/ESF digital trunk interfaces
Computer to PBX interfaces (DMI and CPI)
High speed computer to computer data links
TxSF
C2i
F0i
RxSF
DSTo
DSTi
CSTi0
CSTi1
CSTo
C1.5i
ST-BUS
Timing
Circuitry
1544-2048
Two Frame
Elastic
Buffer
DS1
LINK
INTERFACE
2048 - 1544
Converter
Serial
Control
Interface
Transmitter
RxFDLClk
RxFDL
TxFDLClk
TxFDL
OUTA
OUTB
RxA
RxT
LOS
RxR
RxB
Data
Interface
Receiver
ABCD
Signalling RAM
VDD
XCtl
XSt
Control
Logic
Phase
Detector
Clock
Extractor
DS1
Counter
E1.5o
E8Ko
VSS
Figure 1 - Functional Block Diagram
4-55
MH89760B
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
LOS
NC
TxFDL
NC
TxFDLClk
VSS
RxFDLClk
DSTo
RxFDL
OUTB
C1.5i
RxSF
TxSF
OUTA
NC
NC
NC
VSS
Preliminary Information
NC
E1.5o
VDD
RxA
RxT
RxR
RxB
NC
CSTi1
CSTi0
E8Ko
XCtl
XSt
CSTo
NC
DSTi
C2i
E1.5o
F0i
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Figure 2 - Pin Connections
Pin Description
Pin #
2
3
4
5
6
7
8
9
10
11
12
Name
NC
E1.5o
V
DD
RxA
RxT
RxR
RxB
NC
CSTi1
CSTi0
E8Ko
No Connection.
1.544 MHz Extracted Clock (Output):
This clock is extracted by the device from the
received DS1 signal. It is used internally to clock in data received at RxT and RxR.
System Power Supply.
+5V.
Received A (Output):
The bipolar DS1 signal received by the device at RxR and RxT is
converted to a unipolar format and output at this pin.
Receive Tip and Ring Inputs:
Bipolar split phase inputs designed to be connected
directly to the input transformer. Impedance to ground is approximately 1kΩ.
Impedance between pins=430Ω.
Received B (Output):
The bipolar DS1 signal received by the device at RxR and RxT is
converted to a unipolar format and output at this pin.
No Connection.
Control ST-BUS Input #1:
A 2048 kbit/s serial control stream which carries 24 per-
channel control words.
Control ST-BUS Input #0:
A 2048 kbit/s serial control stream that contains 24 per
channel control words and two master control words.
8 kHz Extracted Clock (Output):
This is an 8 kHz output generated by dividing the
extracted 1.544 MHz clock by 193 and aligning it with the received DS1 frame. The 8
kHz signal can be used for synchronizing system clocks to the extracted 1.544 MHz
clock. When digital loopback is enabled, the 8kHz is derived from C1.5.
External Control (Output):
This is an uncommitted external output pin which is set or
reset via bit 3 in Master Control Word 1 on CSTi0. The state of XCtl is updated once per
frame.
External Status (Schmitt Trigger Input):
The state of this pin is sampled once per
frame and the status is reported in bit 5 of Master Status Word 2 on CSTo.
Control ST-BUS Output:
This is a 2048 kbit/s serial control stream which provides the
24 per-channel status words, and two master status words.
No Connection.
Description
13
XCtl
14
15
16
XSt
CSTo
NC
4-56
Preliminary Information
Pin Description (Continued)
Pin #
17
18
Name
DSTi
C2i
Description
MH89760B
Data ST-BUS Input:
This pin accepts a 2048 kbit/s serial stream which contains the 24
PCM or data channels to be transmitted on the T1 trunk.
2.048 MHz System Clock (Input):
This is the master clock for the ST-BUS section of
the chip. All data on the ST-BUS is clocked in on the falling edge of C2i and out on the
rising edge.
1.544 MHz Extracted Clock (Output):
Internally connected to Pin 3.
Frame Pulse Input:
This is the frame synchronization signal which defines the
beginning of the 32 channel ST-BUS frame.
System ground.
No Connection.
Output A (Open Collector Output):
This is the output of the DS1 transmitter circuit. It is
suitable for use with an external pulse transformer to generate the transmit bipolar line
signal.
Transmit Superframe Pulse Input:
A low pulse applied at this pin will determine the
start of the next transmit superframe as illustrated in Figure 20. The device will free run if
this pin is held high.
Received Superframe Pulse Output:
A pulse output on this pin indicates that the next
frame of data on the ST-BUS is from frame 1 of the received superframe. The period is
12 frames long in D3/D4 modes and 24 frames in ESF mode. Active only when device is
synchronized to received DS1 signal.
1.544 MHz Clock Input:
The rising edge of this clock is used to output data on OUTA,
OUTB. C1.5i must be phase-locked to the C2i system clock.
Output B (Open Collector Output):
This is the output of the DS1 transmitter circuit. It is
suitable for use with an external pulse transformer to generate the transmit bipolar line
signal.
Received Facility Data Link (Output):
A 4 kbit/s serial output stream that is
demultiplexed from the FDL bits in ESF mode, or the received F
S
bit pattern when in
SLC96 mode. It is clocked out on the rising edge of RxFDLClk.
Data ST-BUS Output:
A 2048 kbit/s serial output stream which contains the 24 PCM or
data channels received from the DS1 line.
Receive Facility Data Link Clock Output:
A 4 kHz clock used to output FDL
information on RxFDL. Data is clocked out on the rising edge of the clock.
No Connection.
Transmit Facility Data Link Clock Output:
A 4 kHz clock used to input FDL
information on TxFDL. Data is clocked in on the rising edge of the clock.
No Connection.
Transmit Facility Data Link (Input)
:
A 4 kbit/s serial input stream that is muxed into the
FDL bits in the ESF mode, or the F
S
pattern when in SLC96 mode. It is clocked in on the
rising edge of TxFDLClk.
No Connection.
Loss of Signal (Output):
This pin goes high when 128 contiguous ZEROs are received
on the RxT and RxR inputs. When LOS is high, RxA and RxB are forced high. LOS is
reset when 48 ones are received in a two T1-frame period.
No Connection.
No Connection.
4-57
19
20
21
22-24
25
E1.5o
F0i
V
SS
NC
OUTA
26
TxSF
27
RxSF
28
29
C1.5i
OUTB
30
RxFDL
31
32
33
34
35
36
DSTo
RxFDLClk
V
SS
TxFDLClk
NC
TxFDL
37
38
NC
LOS
39
40
NC
NC
MH89760B
4-58
6
7
8
X
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
9
10
11
12
X
13
14
15
16
X
17
18
19
20
X
21
22
23
24
X
25
26
27
28
X
29
30
31
5
6
DSTi
0
X
1
2
3
4
X
5
DS1
1
2
3
4
ST-BUS CHANNEL VERSUS DS1 CHANNEL TRANSMITTED
6
7
8
X
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
9
10
11
12
X
13
14
15
16
X
17
18
19
20
X
21
22
23
24
X
25
26
27
28
X
29
30
31
DSTo
0
X
5
6
1
2
3
4
X
5
DS1
1
2
3
4
22
23
24
ST-BUS CHANNEL VERSUS DS1 CHANNEL RECEIVED
CSTi0
7
X
11
X
15
MC
W1
19
X
23
X
13
14
15
16
17
18
0
1
2
PC PC PC
CW CW CW
1
1
1
6
7
8
9
10
11
12
3
X
4
5
6
PC PC PC
CW CW CW
1
1
1
8
9
10
PC PC PC
CW CW CW
1
1
1
12
13
14
PC PC PC
CW CW CW
1
1
1
16
17
18
PC PC PC
CW CW CW
1
1
1
20
21
22
PC PC PC
CW CW CW
1
1
1
24
25
26
PC PC PC
CW CW CW
1
1
1
19
20
21
27
X
28
29
30
PC PC PC
CW CW CW
1
1
1
22
23
24
31
MC
W2
DS1
1
2
3
4
5
PCCW=Per Channel Control Word, MCW1/2=Master Control Word 1/2
ST-BUS CHANNEL VERSUS DS1 CHANNEL CONTROLLED
CSTi1
7
X
11
X
15
X
8
9
10
PC PC PC
CW CW CW
2
2
2
12
13
14
PC PC PC
CW CW CW
2
2
2
16
17
18
PC PC PC
CW CW CW
2
2
2
13
14
15
10
11
12
7
8
9
0
1
2
PC PC PC
CW CW CW
2
2
2
6
3
X
4
5
6
PC PC PC
CW CW CW
2
2
2
19
X
20
21
22
PC PC PC
CW CW CW
2
2
2
16
17
18
23
X
24
25
26
PC PC PC
CW CW CW
2
2
2
19
20
21
27
X
28
29
30
PC PC PC
CW CW CW
2
2
2
22
23
24
31
X
DS1
1
2
3
4
5
PCCW=Per Channel Control Word
ST-BUS CHANNEL VERSUS DS1 CHANNEL CONTROLLED
7
X
7
8
9
10
11
8
9
10
PCS PCS PCS
W
W
W
11
X
15
12
13
14
16
17
18
PCS PCS PCS MS PCS PCS PCS
W
W
W W1 W
W
W
12
13
14
15
19
X
20
21
22
PCS PCS PCS
W
W
W
16
17
18
23
X
24
25
26
PCS PCS PCS
W
W
W
19
20
21
27
X
31
28
29
30
PCS PCS PCS MS
W
W
W W2
22
23
24
CSTo
3
0
1
2
PCS PCS PCS PS
W
W
W W
6
4
5
6
PCS PCS PCS
W
W
W
DS1
1
2
3
4
5
PCSW=Per Channel Status Word, PSW=Phase Status Word, MSW=Master Status Word
ST-BUS VERSUS DS1 CHANNEL STATUS
Figure 3 - ST-BUS Channel Allocations
Preliminary Information
X = UNUSED
Preliminary Information
Functional Description
The MH89760B is a thick film hybrid solution for a T1
interface.
All of the formatting and signalling
insertion and detection is done by the device.
Various programmable options in the device include:
ESF, D3/D4 or SLC-96 mode, common channel or
robbed bit signalling, zero code suppression, alarms,
and local and remote loopback. The MH89760B also
has built in bipolar line drivers and receivers and a
clock extraction circuit.
All data and control information is communicated to
the MH89760B via 2048 kbit/s serial streams
conforming to Mitel’s ST-BUS format.
The ST-BUS is a TDM serial bus that operates at
2048 kbits/s. The serial streams are divided into 125
µsec frames that are made up of 32 8-bit channels. A
serial stream that is made up of these 32 8 bit
channels is known as an ST-BUS stream, and one of
these 64 kbit/s channels is known as an ST-BUS
channel.
The system side of the MH89760B is made up of ST-
BUS inputs and outputs, i.e., control inputs and
outputs (CSTi/o) and data inputs and outputs
(DSTi/o). These signals are functionally represented
in Figure 32. The DS1 line side of the device is made
up of split phase inputs (RxT, RxR) and outputs
(OUTA, OUTB) which can be connected to line
coupling transformers. Functional
transmit
and
receive timing is shown in Figures 33 and 34.
Data for transmission on the DS1 line is clocked
serially into the device at the DSTi pin. The DSTi pin
accepts a 32 channel time division multiplexed ST-
BUS stream. Data is clocked in with the falling edge
of the C2i clock. ST-BUS frame boundaries are
defined by the frame pulse applied at the F0i pin.
Only 24 of the available 32 channels on the ST-BUS
serial stream are actually transmitted on the DS1
side. The unused 8 channels are ignored by the
device.
Data received from the DS1 line is clocked out of the
device in a similar manner at the DSTo pin. Data is
clocked out on the rising edge of the C2i clock. Only
24 of the 32 channels output by the device contain
the information from the DS1 line. The DSTo pin is,
however, actively driven during the unused channel
timeslots. Figure 3 shows the correspondence
between the DS1 channels and the ST-BUS
channels.
All control and monitoring of the device is
accomplished through two ST-BUS serial control
MH89760B
inputs and one serial control output. Control ST-BUS
input number 0 (CSTi0) accepts an ST-BUS serial
stream which contains the 24 per channel control
words and two master control words. The per channel
control words relate directly to the 24 information
channels output on the DS1 side. The master control
words affect operation of the whole device. Control
ST-BUS input number 1 (CSTi1) accepts an ST-BUS
stream containing the A, B, C and D signalling bits.
The relationship between the CSTi channels and the
controlled DS0 channels is shown in Figure 3. Status
and signalling information is received from the device
via the control ST-BUS output (CSTo). This serial
output stream contains two master status words, 24
per channel status words and one Phase Status
Word. Figure 3 shows the correspondence between
the received DS1 channels and the status words.
Detailed information on the operation of the control
interface is presented below.
Programmable Features
The main features in the device are programmed
through two master control words which occupy
channels 15 and 31 in Control ST-BUS input stream
number 0 (CSTi0). These two eight bit words are
used to:
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Select the different operating modes of the
device ESF, D3/D4 or SLC-96.
Activate the features that are needed in a
certain application; common channel signalling,
zero code suppression, signalling debounce,
etc.
Turn on in service alarms, diagnostic loop
arounds, and the external control function.
•
Tables 1 and 2 contain a complete explanation of the
function of the different bits in Master Control Words
1 and 2.
Major Operating Modes
The major operating modes of the device are
enabled by bits 2 and 4 of Master Control Word 2.
The Extended Superframe (ESF) mode is enabled
when bit 4 is set high. Bit 2 has no effect in this
mode. The ESF mode enables the transmission of
the S bit pattern shown in Table 3. This includes the
frame/superframe pattern, the CRC-6, and the
Facility Data Link (FDL). The device generates the
frame/multiframe pattern and calculates the CRC for
each superframe. The data clocked into the device
on the TxFDL pin is incorporated into the FDL. ESF
mode will also insert A, B, C and D signalling bits into
the 24 frame multiframe. The DS1 frame begins after
approximately 25 periods of the C1.5i clock from the
F0i frame pulse.
4-59
