NXP Semiconductors
Data Sheet: Technical Data
Document Number: KL03P24M48SF0
Rev. 5.1 08/2017
Kinetis KL03 32 KB Flash
48 MHz Cortex-M0+ Based Microcontroller
Supports ultra low power 48 MHz devices with up to 32 KB
Flash.
World's smallest MCU based on ARM
®
technology. Ideal
solution for Internet of Things edge nodes design with ultra small
form factor and ultra low power consumption. The products
offers:
• Tiny footprint packages, including 1.6 x 2.0 mm
2
WLCSP
• Run power consumption as low as 50 µA/MHz
• Static power consumption as low as 2.2 µA with 7.5 µs
wakeup time for full retention and lowest static mode down
to 77 nA in deep sleep
• Highly integrated peripherals, including new boot ROM and
high accurate internal voltage reference, etc
MKL03ZxxVFG4
MKL03ZxxVFK4
MKL03Z32CAF4R
MKL03Z32CBF4R
16-pin QFN (FG)
3 x 3 x 0.65 Pitch 0.5
mm
24-pin QFN (FK)
4 x 4 x 0.65 Pitch 0.5
mm
20 WLCSP
2 x 1.61 x 0.56 Pitch 0.4 mm(AF) 2 x 1.61 x
0.32 Pitch 0.4 mm (BF)
Core
• ARM
®
Cortex
®
-M0+ core up to 48 MHz
Memories
• Up to 32 KB program flash memory
• 2 KB SRAM
• 8 KB ROM with build-in bootloader
• 16 bytes regfile
System peripherals
• Nine low-power modes to provide power optimization
based on application requirements
• COP Software watchdog
• Low-leakage wakeup unit
• SWD debug interface and Micro Trace Buffer
• Bit Manipulation Engine
Clocks
• 48 MHz high accuracy internal reference clock
• 8/2 MHz low power internal reference clock
• 32 kHz to 40 kHz crystal oscillator
• 1 kHz LPO clock
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C for QFN
packages; -40 to 85°C for WLCSP packages
Human-machine interface
• General-purpose input/output up to 22
Communication interfaces
• One 8-bit SPI module
• One LPUART module
• One I2C module supporting up to 1 Mbit/s, with
double buffer
Analog Modules
• 12-bit SAR ADC with internal voltage reference, up
to 818 ksps and 7 channels
• High-speed analog comparator containing a 6-bit
DAC and programmable reference input
• 1.2 V voltage reference (Vref)
Timers
• Two 2-channel Timer/PWM modules
• One low-power timer
• Real time clock
Security and integrity modules
• 80-bit unique identification number per chip
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information1
Part Number
Flash (KB)
MKL03Z8VFG4(R)
MKL03Z16VFG4(R)
MKL03Z32VFG4(R)
MKL03Z32CAF4R
MKL03Z32CBF4R
MKL03Z8VFK4(R)
MKL03Z16VFK4(R)
MKL03Z32VFK4(R)
8
16
32
32
32
8
16
32
Memory
SRAM (KB)
2
2
2
2
2
2
2
2
14
14
14
18
18
22
22
22
Maximum number of I\O's
1. To confirm current availability of ordererable part numbers, go to
http://www.nxp.com
and perform a part number search.
Related Resources
Type
Selector Guide
Product Brief
Reference
Manual
Data Sheet
Chip Errata
Package
drawing
Description
The Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
Resource
Solution Advisor
The Product Brief contains concise overview/summary information to KL03PB
1
enable quick evaluation of a device for design suitability.
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
The Data Sheet includes electrical characteristics and signal
connections.
The chip mask set Errata provides additional or corrective
information for a particular device mask set.
Package dimensions are provided in package drawings.
KL03P24M48SF0RM
1
KL03P24M48SF0
1
KL03Z_xN86K
2
QFN 16-pin: 98ASA00525D
1
QFN 24-pin: 98ASA00602D
1
WLCSP 20-pin: 98ASA00676D
1
WLCSP 20-pin (ultra thin):
98ASA00964D
1
1. To find the associated resource, go to
http://www.nxp.com
and perform a search using this term.
2. To find the associated resource, go to
http://www.nxp.com
and perform a search using this term with the “x” replaced by
the revision of the device you are using.
Figure 1
shows the functional modules in the chip.
2
NXP Semiconductors
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
Kinetis KL03 Family
ARM Cortex-M0+
Core
SWD
interfaces
Interrupt
controller
System
Internal
watchdog
Memories and
Memory Interfaces
Program
flash
Clocks
Low
frequency
oscillator
BME
RAM
Internal
reference
clocks
LPO
ROM
MTB
Register
file
and Integrity
Unique ID
Security
Analog
12-bit ADC
x1
Timers
Timers
2x2ch
Low Power
Timer
Communication
Interfaces
I
C
x1
Low power
UART
x1
SPI
x1
2
Human-Machine
Interface (HMI)
GPIOs
with
interrupt
Analog
comparator
with
6-bit DAC
x1
RTC
VREF
Figure 1. Functional block diagram
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
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NXP Semiconductors
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 6
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................7
2.2.1 Voltage and current operating requirements....... 7
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors..... 24
2.2.7 EMC Radiated Emissions Web Search
Procedure boilerplate.......................................... 25
2.2.8 Capacitance attributes.........................................25
2.3 Switching specifications...................................................25
2.3.1 Device clock specifications..................................25
2.3.2 General switching specifications......................... 26
2.4 Thermal specifications..................................................... 26
2.4.1 Thermal operating requirements......................... 26
2.4.2 Thermal attributes................................................27
3 Peripheral operating requirements and behaviors.................. 27
3.1 Core modules.................................................................. 27
3.1.1 SWD electricals .................................................. 28
3.2 System modules.............................................................. 29
3.3 Clock modules................................................................. 29
3.3.1 MCG-Lite specifications.......................................29
3.3.2 Oscillator electrical specifications........................30
3.4 Memories and memory interfaces................................... 31
3.4.1 Flash electrical specifications.............................. 31
3.5 Security and integrity modules........................................ 33
3.6 Analog............................................................................. 33
3.6.1 ADC electrical specifications............................... 33
3.6.2 CMP and 6-bit DAC electrical specifications....... 37
3.6.3 Voltage reference electrical specifications.......... 39
3.7 Timers..............................................................................40
3.8 Communication interfaces............................................... 40
3.8.1 SPI switching specifications................................ 41
3.8.2 Inter-Integrated Circuit Interface (I2C) timing...... 45
3.8.3 UART...................................................................47
Dimensions............................................................................. 47
4.1 Obtaining package dimensions....................................... 47
Pinout...................................................................................... 48
5.1 KL03 signal multiplexing and pin assignments................ 48
5.2 KL03 pinouts....................................................................49
Ordering parts......................................................................... 51
6.1 Determining valid orderable parts....................................51
Part identification.....................................................................51
7.1 Description.......................................................................51
7.2 Format............................................................................. 52
7.3 Fields............................................................................... 52
7.4 Example...........................................................................52
Terminology and guidelines.................................................... 53
8.1 Definition: Operating requirement....................................53
8.2 Definition: Operating behavior......................................... 53
8.3 Definition: Attribute.......................................................... 54
8.4 Definition: Rating............................................................. 54
8.5 Result of exceeding a rating............................................ 55
8.6 Relationship between ratings and operating
requirements....................................................................55
8.7 Guidelines for ratings and operating requirements..........55
8.8 Definition: Typical value...................................................56
8.9 Typical value conditions.................................................. 57
9 Revision history.......................................................................57
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NXP Semiconductors
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
Ratings
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol
T
STG
T
SDR
Description
Storage temperature
Solder temperature, lead-free
Min.
–55
—
Max.
150
260
Unit
°C
°C
Notes
1
2
1. Determined according to JEDEC Standard JESD22-A103,
High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020,
Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. QFN packages moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
—
Max.
3
Unit
—
Notes
1
1. Determined according to IPC/JEDEC Standard J-STD-020,
Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
Table 3. WLCSP packages moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
—
Max.
1
Unit
—
Notes
1
1. Determined according to IPC/JEDEC Standard J-STD-020,
Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 4. ESD handling ratings
Symbol
V
HBM
V
CDM
I
LAT
Description
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device
model
Latch-up current at ambient temperature of 105 °C
Min.
–2000
–500
–100
Max.
+2000
+500
+100
Unit
V
V
mA
Notes
1
2
3
Kinetis KL03 32 KB Flash, Rev. 5.1 08/2017
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NXP Semiconductors
