ML144110
ML144111
Digital–to–Analog Converters
with Serial Interface
CMOS LSI
Legacy Device:
Motorola/Freescale MC144110, MC144111
The ML144110 and ML144111 are low–cost 6–bit D/A converters with
serial interface ports to provide communication with CMOS microproces-
sors and microcomputers. The ML144110 contains six static D/A convert-
ers; the ML144111 contains four converters.
Due to a unique feature of these DACs, the user is permitted easy scaling
of the analog outputs of a system. Over a 5 to 15 V supply range, these
DACs maybe directly interfaced to CMOS MPUs operating at 5 V
.
•
•
•
•
•
•
•
•
Direct R–2R Network Outputs
Buffered Emitter–Follower Outputs
Serial Data Input
Digital Data Output Facilitates Cascading
Direct Interface to CMOS µP
Wide Operating Voltage Range: 4.5 to 15 V
Wide Operating Temperature Range: TA = 0 to 85°C
Software Information is Contained in Document M68HC11RM/AD
18
1
MC144110
P DIP 18 = VP
PLASTIC DIP
CASE 707
20
1
SO 20W = -6P
SOG PACKAGE
CASE 751D
MC144111
P DIP 14 = CP
PLASTIC DIP
CASE 646
14
BLOCK DIAGRAM
VDD
Q1 OUT
Qn Rn
R1 OUT OUT OUT
1
16
1
SO 16W = -5P
SOG PACKAGE
CASE 751G
2R
R
2R
2R
R
2R
R
2R
R
2R
R
2R
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 18
MC144110P
ML144110VP
SO 20W
MC144110DW
ML144110-6P
P DIP 14
MC144111P
ML144111CP
SO 16W
MC144111DW
ML144111-5P
HEX BUFFER (INVERTING)
Note:
Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from
ML
to
MLE.
ENB
C
HEX LATCH
CLK
C
*
C
D
6–BIT SHIFT REGISTER
Dout
D Q
Din
* Transparent Latch
Page 1 of 8
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ML144110, ML144111
LANSDALE Semiconductor, Inc
PIN ASSIGNMENTS
ML144110VP
Din
Q1 Out
R1 Out
Q2 Out
R2 Out
Q3 Out
R3 Out
ENB
VSS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
VDD
Dout
R6 Out
Q6 Out
R5 Out
Q5 Out
R4 Out
Q4 Out
CLK
Din
Q1 Out
R1 Out
Q2 Out
R2 Out
Q3 Out
R3 Out
ENB
VSS
NC
ML144110-6P
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
Dout
R6 Out
Q6 Out
R5 Out
Q5 Out
R4 Out
Q4 Out
CLK
NC
ML144111CP
Din
Q1 Out
R1 Out
Q2 Out
R2 Out
ENB
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
Dout
R4 Out
Q4 Out
R3 Out
Q3 Out
CLK
Din
Q1 Out
R1 Out
Q2 Out
R2 Out
ENB
VSS
NC
ML144111-5P
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
Dout
R4 Out
Q4 Out
R3 Out
Q3 Out
CLK
NC
NC = NO CONNECTION
Page 2 of 8
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ML144110, ML144111
LANSDALE Semiconductor, Inc
MAXIMUM RATINGS*
(Voltages referenced to VSS)
Parameter
DC Supply Voltage
Input Voltage, All Inputs
DC Input Current, per Pin
Power Dissipation (Per Output)
TA = 70°C, MC144110
MC144111
TA = 85°C, MC144110
MC144111
Power Dissipation (Per Package)
TA = 70°C, MC144110
MC144111
TA = 85°C, MC144110
MC144111
Storage Temperature Range
Symbol
VDD
Vin
I
POH
30
50
10
20
PD
100
150
25
50
Tstg
– 65 to + 150
°C
mW
Value
– 0.5 to + 18
– 0.5 to VDD + 0.5
±
10
Unit
V
V
mA
mW
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields; however, it is ad-
vised that precautions be taken to avoid
application of voltage higher than maximum
rated voltages to this high–impedance circuit.
For proper operation it is recommended that
Vin and Vout be constrained to the range VSS
≤
(Vin or Vout)
≤V
DD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD).
* Maximum Ratings are those values beyond which damage to the device may occur.
ELECTRICAL CHARACTERISTICS
(Voltages referenced to VSS, TA = 0 to 85°C unless otherwise indicated)
Symbol
VIH
Parameter
High–Level Input Voltage (Din, ENB, CLK)
Test Conditions
VDD
5
10
15
5
10
15
Vout = VDD – 0.5 V
Vout = 0.5 V
Iout = 0
µA
Vin = VDD or 0 V
See Figure 1
5
5
15
15
15
5
10
15
5
10
15
—
15
—
—
Min
3.0
3.5
4
—
—
—
– 200
200
—
—
—
—
—
—
19
39
58
—
—
40
0.4
Max
—
—
—
0.8
0.8
0.8
—
—
12
8
±
1
100
200
300
137
274
411
1
10
—
0.7
Unit
V
VIL
Low–Level Input Voltage (Din, ENB, CLK)
V
IOH
IOL
IDD
Iin
Vnonl
High–Level Output Current (Dout)
Low–Level Output Current (Dout)
Quiescent Supply Current
ML144110
ML144111
µA
µA
mA
µA
mV
Input Leakage Current (Din, ENB, CLK)
Nonlinearity Voltage (Rn Out)
Vstep
Step Size (Rn Out)
See Figure 2
mV
Voffset
IE
hFE
VBE
Offset Voltage from VSS
Emitter Leakage Current
DC Current Gain
Base–to–Emitter Voltage Drop
Din = $00, See Figure 1
VRn Out = 0 V
IE = 0.1 to 10.0 mA
TA = 25°C
IE = 1.0 mA
LSB
µA
—
V
Page 3 of 8
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ML144110, ML144111
LANSDALE Semiconductor, Inc
SWITCHING CHARACTERISTICS
(Voltages referenced to VSS, TA = 0 to 85°C, CL = 50 pF, Input tr = tf = 20 ns unless otherwise indicated)
Symbol
twH
Parameter
Positive Pule Width, CLK (Figures 3 and 4)
VDD
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5 – 15
5 – 15
Min
2
1.5
1
5
3.5
2
5
3.5
2
1000
750
500
5
3.5
2
5
3.5
2
—
—
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
7.5
Unit
µs
twL
Negative Pulse Width, CLK (Figure 3 and 4)
µs
tsu
Setup Time, ENB to CLK (Figures 3 and 4)
µs
tsu
Setup Time, Din to CLK (Figures 3 and 4)
ns
th
Hold Time, CLK to ENB (Figures 3 and 4)
µs
th
Hold Time, CLK to Din (Figures 3 and 4)
µs
tr, tf
Cin
Input Rise and Fall Times
Input Capacitance
µs
pF
OUTPUT VOLTAGE @ Rn Out, % (VDD – VSS )
100
75
Vnonl
ACTUAL
50
IDEAL
25
Voffset
0
0
$00
15
$0F
31
$1F
PROGRAM STEP
47
$2F
63
$3F
LINEARITY ERROR
(integral linearity). A measure of how
straight a device’s transfer function is, it indicates the worst–case
deviation of linearity of the actual transfer function from the best–
fit straight line. It is normally specified in parts of an LSB.
Figure 1. D/A Transfer Function
Page 4 of 8
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ML144110, ML144111
LANSDALE Semiconductor, Inc
VRn OUT
STEP
SIZE
Step Size =
VDD
±
0.75 VDD
64
64
(For any adjacent pair of digital numbers)
DIGITAL NUMBER
Figure 2. Definition of Step Size
ENB
50%
tsu
CLK
50%
C1
twH
twL
C2
CN
th
Din
tsu
D1
th
D2
DN
Figure 3. Serial Input, Positive Clock
ENB
tsu
CLK
C1
twL
twH
C2
CN
th
Din
D1
tsu
D2
th
DN
Figure 4. Serial Input, Negative Clock
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