FEDL227XX-06
Issue Date: Oct.16, 2013
ML2272X-XXX/ML2276X-XXX
Speech Synthesis LSI with Built-in P2ROM Including Speech-Speed Conversion/Pitch Conversion Functions
GENERAL DESCRIPTION
The ML2272X(ML22725/ML22724/ML22723-XXX) and ML2276X(ML22765/ML22764/ML22763-XXX) are
speech synthesis LSIs with built-in P2ROM that stores speech data.
These LSIs include speech speed conversion, pitch conversion, edit ROMs, ADPCM2 decoders, 16-bit DA
converters, low pass filters, and monaural speaker amplifiers. The ML2272X supports the synchronous serial
interface and the ML2276X supports the I2C interface. By integrating all the functions required for speech
output into a single chip, these LSIs can be more easily incorporated in compact portable devices.
Built-in memory capacity and maximum vocal reproduction time:
the following table (in 4-bit ADPCM2 mode)
Product name
ML22725-XXX/ML22765
ML22724-XXX/ML22764
ML22723-XXX/ML22763
ROM capacity
16 Mbits
8 Mbits
4 Mbits
Maximum vocal reproduction time (sec) *
F
S
= 16 kHz
F
S
= 32 kHz
F
S
= 8.0 kHz
522
261
130
260
130
64
129
64
32
(*: Speech -speed or pitch conversion functions is not used.)
4-bit ADPCM2
8-bit Nonlinear PCM
8-bit PCM, 16-bit PCM
Can be specified for each phrase.
4.0 / 5.3 / 6.4 / 8.0 / 10.6 / 12.0 / 12.8 / 16.0 / 21.3 / 24.0 / 25.6 / 32.0 /
Sampling frequency(F
S
):
48.0 kHz
F
S
can be specified for each phrase.
Built-in low-pass filter and 16-bit DA converter
Speaker driving amplifier:
0.7 W (8 , DV
DD
=5 V, Ta=25C)
Analog input: 2ch (internal: 1ch, external: 1ch)
CPU command interface:
3-wired serial clock-synchronized (ML2272X)
I2C interface (ML2276X)
Maximum number of phrases:
4096 phrases, from 000h to 3FFh (1024 phrases/bank)
Memory bank switching:
Enabled between bank 1 and bank 4 using the SEL0 and SEL1 pins.
Volume control:
32 levels (OFF is included) can be set by CVOL command.
50 levels (OFF is included) can be set by AVOL command.
Repeat function:
LOOP commands
Speech speed conversion function
0.50
to
2.00
(150 levels: 0.01 step)
Pitch conversion function
20%
(40 levels: 1% step width)
Source oscillation frequency:
4.096 MHz
Power supply voltage:
2.7 to 3.6V / 4.5 to 5.5 V
Operating temperature range:
–40C to +85C
Package:
30-pins plastic SSOP (SSOP30-P-56-0.65-K-MC)
Product name:
ML22725-xxxMB,ML22724-xxxMB, ML22723-xxxMB
ML22765-xxxMB,ML22764-xxxMB, ML22763-xxxMB
(xxx: ROM code No.)
voice synthesis method:
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FEDL227XX-06
ML2272X-XXX/ML2276X-XXX
The table below summarizes the differences from the ML2216 and ML22800 series.
Parameter
CPU interface
Playback method
Maximum number
of phrases
Sampling frequency
(kHz)
ML2216
Serial
4-bit ADPCM2
8-bit straight PCM
8-bit nonlinear PCM
16-bit straight PCM
256
4.0/5.3/6.4/
8.0/10.6/12.8
16.0
4.096MHz
(with a built-in crystal
oscillator circuit)
12 bits
3rd order comb filter
Built-in 0.3W
(8, DV
DD
= 5 V)
No
Yes
16 levels
Yes
20 ms to 1024 ms
(4 ms/step)
Yes
No
ML22800 series
ML22725/ML22724/
ML22723-XXX
ML22765/ML22764/
ML22763-XXX
I2C
1024 (256/bank)
4096 (1024/bank)
4.0/5.3/6.4/8.0/
10.6/12.0/12.8/
16.0/21.3/24.0/
25.6/32.0/48.0
16 bits
FIR interpolation filter
Built-in 0.7W
(8, DV
DD
= 5 V)
Yes
32 levels
Clock frequency
D/A converter
Low-pass filter
Speaker driving
amplifier
Speech speed/pitch
conversion
Edit ROM function
Volume control
Silence insertion
Repeat function
Interval at which a
seam is silent
during continuous
playback (Note)
Power supply
voltage
Package
12 bits
3rd order comb filter
No
2.7 V to 5.5 V
44-pin QFP
2.7 V to 3.6 V
30-pin SSOP
2.7 V to 5.5 V
*1: Continuous playback as shown below is possible.
1 phrase
1 phrase
No silence interval
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FEDL227XX-06
ML2272X-XXX/ML2276X-XXX
BLOCK DIAGRAMS
(ML22725/ML22724/ML22723-XXX)
DV
DD
DGND
V
DDL
V
DDR
Phrase Address
Latch
21/20/19bit
Address Counter
ADPCM Synthesizer
Address Controller
21/20/19bit Multiplexer
16/8/4Mbit ROM
CSB
SCK
SI
SO
CBUSYB
DIPH
SEL0
SEL1
TESTI0,1
TESTO
RESETB
XT
XTB
PCM Synthesizer
I/O
Interface
LPF
Timing
Controller
16bit DAC
SP-AMP
OSC
PLL
SPV
DD
SPGND
SPM SPP
AIN
(ML22765/ML22764/ML22763-XXX)
DV
DD
DGND
V
DDL
V
DDR
Phrase Address
Latch
21/20/19bit
Address Counter
ADPCM Synthesizer
Address Controller
21/20/19bit Multiplexer
16/8/4Mbit ROM
SDA2-0
SCL
SDA
CBUSYB
SEL0
SEL1
TESTI0,1
TESTO
RESETB
I/O
Interface
PCM Synthesizer
LPF
Timing
Controller
16bit DAC
XT
XTB
SP-AMP
OSC
PLL
SPV
DD
SPGND
SPM SPP
AIN
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FEDL227XX-06
ML2272X-XXX/ML2276X-XXX
PIN CONFIGURATIONS (TOP VIEW)
ML22725/ML22724/ML22723-XXXMB (Synchronous serial interface)
AIN
TESTI0
RESETB
TESTO
DIPH
SEL0
SEL1
DGND
CSB
SCK
SI
SO
CBUSYB
DGND
XT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SPM
SPP
SPGND
SPV
DD
DGND
SG
TESTI1
V
DDR
DV
DD
V
DDL
NC
DGND
NC
DV
DD
XTB
NC: No Connection
30-Pin Plastic SSOP
ML22765/ML22764/ML22763-XXXMB (I2C interface)
AIN
TESTI0
RESETB
TESTO
SAD0
SEL0
SEL1
DGND
SAD1
SCL
SDA
SAD2
CBUSYB
DGND
XT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SPM
SPP
SPGND
SPV
DD
DGND
SG
TESTI1
V
DDR
DV
DD
V
DDL
NC
DGND
NC
DV
DD
XTB
NC: No Connection
30-Pin Plastic SSOP
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FEDL227XX-06
ML2272X-XXX/ML2276X-XXX
PIN DESCRIPTION (COMMON TO ALL PRODUCTS)
Pin
1
2
Symbol
AIN
TESTI0
I/O
I
I
Initial value
Description
(*1)
0
Input pin for speaker amplifier.
Input pin for testing.
0
Fix this pin to “L” level (DGND level). This pin has a pull-down resistor
built in.
Input pin for reset..
At the “L” level, the LSI enters initial state. During reset, the entire
circuitry stops and enters power down state. Input “L” level when
0
power is supplied. After the power supply voltage is stable, drive this
(*2)
pin to “H” level. Then the entire circuitry can be powered up.
This pin has a pull-up resistor built in.
Output pin for testing.
Hi-Z
Leave this pin open.
Memory bank switching pins.
0
Fix these pins to “L” level when the memory bank function is not used.
Digital ground pin. Also serves as a ground pin for the internal
—
memory.
Output pin for command processing status..
1
This pin outputs “L” level during command processing. Any command
should be entered when this pin is “H” level.
Connect to the crystal or ceramic resonator.
A feedback resistor around 1 M is built in between this pin and the
0
XTB pin. Use this pin if need to use an external clock.
If the resonator is used, connect it as close to this pin as possible.
Connects to the crystal or ceramic resonator.
1
When to use an external clock, leave this pin open.
If the resonator is used, connect it as close to this pin as possible.
Power supply pins for logic circuitry.
—
Connect a capacitor of 0.1
F
or more between these pins and DGND
pins.
—
No-connected pins. Leave these pins open.
Regulator output pin for internal logic circuitry.
0
Connect a capacitor recommended between this pin and DGND pin.
Regulator output pin for Built-in ROM.
0
Connect a capacitor recommended between this pin and DGND pin.
Input pin for testing.
0
Fix this pin to “L” level (DGND level). This pin has a pull-down resistor
built in.
Reference voltage output pin for the speaker amplifier built-in.
0
Connect a capacitor recommended between this pin and DGND pin.
Power supply pin for the speaker amplifier.
—
Connect a bypass capacitor of 0.1 F or more between this pin and
SPGND pin.
—
Ground pin for the speaker amplifier.
Positive(+) output pin of the speaker amplifier built-in.
0
Serves as the LINE output (*3), if built-in speaker amplifier is not used.
Hi-Z
Negative(-) output pin of the speaker amplifier built-in.
3
RESETB
I
4
6, 7
8, 14,
19, 26
13
TESTO
SEL0
SEL1
DGND
CBUSYB
O
I
—
O
15
XT
I
16
XTB
O
17, 22
18, 20
21
23
24
25
27
28
29
30
DV
DD
N.C
V
DDL
V
DDR
TESTI1
SG
SPV
DD
SPGND
SPP
SPM
—
—
—
—
I
—
—
—
O
O
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