FEDL2257-05
Issue Date: Apr. 25, 2013
ML22Q573-NNNMB/ML22Q573-xxxMB/ML2257X-xxxMB
4-Channel Mixing Speech Synthesis LSI with Built-in FLASH/MASK ROM for Automotive
GENERAL DESCRIPTION
The ML22Q573-NNN, ML22Q573-xxx and ML2257X-xxx are 4-channel mixing speech synthesis LSIs with
built-in FLASH/MASK ROM for voice data. These LSIs incorporate into them an HQ-ADPCM decoder that
enables high sound quality, 16-bit D/A converter, low-pass filter, and 1.0 W monaural speaker amplifier for
driving speakers. Since functions necessary for voice output are all integrated into a single chip, a system can
be upgraded with audio features by only using one of these LSIs.
•
Capacity of internal memory and the maximum voice production time (when HQ-ADPCM
※
1
method used)
Maximum voice production time (sec)
f
sam
= 8.0 kHz
ML22Q573-NNN/-xxx
ML22573-xxx
ML22572-xxx
4 Mbits
2 Mbits
161
79
f
sam
= 16.0 kHz
80
39
f
sam
= 32.0 kHz
40
19
Product name
ROM capacity
FEATURES
Can be specified for each phrase.
HQ-ADPCM / 8-bit non-linear PCM / 8-bit PCM / 16-bit PCM
•
Sampling frequency:
Can be specified for each phrase.
12.0/24.0/48.0 kHz, 8.0 / 16.0/32.0 kHz, 6.4/12.8/25.6 kHz
•
Built-in low-pass filter and 16-bit D/A converter
•
Built-in speaker driver amplifier:
1.0 W, 8Ω (at DV
DD
= 5 V)
•
External analog voice input (built-in analog mixing function)
•
CPU command interface:
Clock synchronous serial interface
•
Maximum number of phrases:
1024 phrases, from 000h to 3FFh
•
Edit ROM
•
Volume control:
CVOL command: Adjustable through 32 levels (including OFF)
AVOL command: Adjustable through 50 levels (including OFF)
•
Repeat function:
LOOP command
•
Channe½ mixing function:
4 channels
•
Power supply voltage detection function: Can be controlled at six levels from 2.7 to 4.0 V (including the
OFF setting)
•
Source oscillation frequency:
4.096 MHz
•
Power supply voltage:
2.7 to 5.5 V
•
Operating temperature range:
–40°C to +105°C
※
2
•
Package:
heat sink type 30-pin plastic SSOP(P-SSOP30-56-0.65-6K-MC)
•Product
name:
ML22Q573-NNNMB
ML22573-xxxMB/ML22572-xxxMB
(“xxx” denotes ROM code number)
※1
HQ-ADPCM is a high sound quality audio compression technology of "Ky's".
“Ｋ½’½” is a Registered trademark of National Universities corporate Kyushu
Institute of Technology
•
Speech synthesis method:
※2
The limitation on the operation time changes by the using condition. (Refer to Page62)
1/66
FEDL2257X-05
ML22Q573/ML2257X
The table below summarizes the differences between the exsisting speech synthesis LSIs (ML225XG and
ML224XXG) and the ML22Q573/ML2257X.
Item
CPU interface
ROM type
ROM capacity
ML225XG
Parallel/Serial
MASK
3/4/6 Mbits
2-bit ADPCM2
4-bit ADPCM2
8-bit straight PCM
8-bit non-linear PCM
16-bit straight PCM
256
4.0/5.3/6.4/8.0/
10.7/12.0/12.8/
16.0/21.3/24.0/
25.6/32.0/48.0
4.096 MHz (has a
crystal oscillator
circuit built-in)
14-bit voltage-type
FIR interpolation
filter
ML224XXG
Serial/I2C
External
Maximum capacity
that can be
connected: 128
Mbits
4-bit ADPCM2
8-bit straight PCM
8-bit non-linear PCM
16-bit straight PCM
1024
←
ML22Q573
Serial
FLASH
4 Mbits
ML2257X
←
MASK
2/4 Mbits
Playback method
HQ-ADPCM
HQ-ADPCM
8-bit straight PCM
8-bit straight PCM
8-bit non-linear PCM 8-bit non-linear PCM
16-bit straight PCM 16-bit straight PCM
←
6.4/8.0/12.0/
12.8/16.0/24.0/
25.6/32.0/48.0
←
←
FIR interpolation
filter
(High-pass
interpolation)
Built-in
1.0 W
(8Ω, DV
DD
= 5 V)
←
←
←
←
←
←
←
←
←
−40°C
to +105°C
←
←
←
Maximum number of
phrases
Sampling frequency
(kHz)
Clock frequency
D/A converter
Low-pass filter
←
16-bit voltage-type
FIR interpolation
filter
(SRC)
Built-in
0.7 W
(8Ω, DV
DD
= 5 V)
4-channel
←
32 levels
←
←
Yes
No
←
←
−40°C
to +85°C
30-pin SSOP
←
←
←
Speaker driving
amplifier
Simultaneous sound
production function
(mixing function)
Edit ROM
Volume control
Silence insertion
Repeat function
External analog
input
External speech
data input
Interval at which a
seam is silent during
continuous playback
Power supply
voltage
Ambient
temperature
Package
No
←
←
←
←
←
←
←
←
←
←
←
←
2-channel
Yes
29 levels
20 to 1024 ms
(4 ms steps)
Yes
No
Yes
No
2.7 V to 5.5 V
−40°C
to +105°C
44-pin QFP
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FEDL2257X-05
ML22Q573/ML2257X
BLOCK DIAGRAM
The block diagrams of the ML22Q573-NNN/ML22Q573-xxx/ML2257X-xxx are shown below.
TESTI0
TESTI1
TESTI2
TESTI3
TESTI4
TESTO
DV
DD
DGND
V
DDL
V
DDR
RESETB
CSB
SCK
SI
SO
CBUSYB
STATUS
ERR
DIPH
TESTI1
Cmd
Analyzer
Address Controller
18/19bit
JTAG
Interface
4Mbit FLASH
PCM Synthesizer
I/O
Interface
PLL
SP-AMP
(AVOL)
Timing
Controller
LPF(CVOL)
16bit DAC
OSC
V
PP
SPV
DD
SPGND
XT XTB
SPM SPP
AIN
SG
Block Diagram of ML22Q573-NNN/ML22Q573-xxx
DV
DD
DGND
V
DDL
Cmd
Analyzer
Address Controller
18/19 bits
2/4-Mbit ROM
RESETB
CSB
SCK
SI
SO
CBUSYB
STATUS
ERR
DIPH
TESTI1
PCM Synthesizer
I/O
Interface
Timing
Controller
LPF (CVOL)
16-bit DAC
PLL
SP-AMP
(AVOL)
OSC
SPV
DD
SPGND
XT XTB
SPM SPP
AIN
SG
Block Diagram of
ML2257X-xxx
3/66
FEDL2257X-05
ML22Q573/ML2257X
PIN CONFIGURATION (TOP VIEW)
●
ML22Q573-NNN/ML22Q573-xxx
AIN
SG
V
DDR
DV
DD
DGND
V
DDL
DIPH
STATUS
ERR
CSB
SCK
SI
SO
CBUSYB
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SPV
DD
SPGND
SPP
SPM
TESTO
TESTI4
TESTI3
TESTI2
TESTI1
TESTI0
RESETB
V
PP
DV
DD
XT
XTB
30-Pin Plastic SSOP
●
ML2257X -xxx
NC：Unused pin
AIN
SG
NC
DV
DD
DGND
V
DDL
DIPH
STATUS
ERR
CSB
SCK
SI
SO
CBUSYB
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SPV
DD
SPGND
SPP
SPM
TESTO
NC
NC
NC
TESTI1
TESTI0
RESETB
NC
DV
DD
XT
XTB
NC：Unused pin
30-Pin Plastic SSOP
4/66
FEDL2257X-05
ML22Q573/ML2257X
PIN DESCRIPTION (1)
Pin
1
2
2
Symbol
AIN
SG
I/O Attribute
I
—
Description
Attribute
analog
analog
3*
V
DDR
4,18
5,15
6
DV
DD
DGND
V
DDL
7
DIPH
8
9
STATUS
ERR
10
11
CSB
SCK
12
SI
13
SO
Speaker amplifier input pin.
Built-in speaker amplifier’s reference voltage output pin.
O
—
Connect a capacitor of 0.1
μF
or more between this pin and
DGND.
2.5 V regulator output pin.
O
—
Acts as an internal power supply (for ROM). Connect a
capacitor of 10
μF
or more between this pin and DGND.
Digital power supply pin.
—
—
Connect a bypass capacitor of 10μF or more between this
pin and DGND.
—
—
Digital ground pin
2.5 V regulator output pin.
O
—
Acts as an internal power supply (for logic). Connect a
capacitor of 10
μF
or more between this pin and DGND.
Serial interface switching pin.
Pin for choosing between rising edges and falling edges as
to the edges of the SCK pulses used for shifting serial data
input to the SI pin into the inside of the LSI.
When this pin is at a “L” level, SI input data is shifted into the
LSI on the rising edges of the SCK clock pulses and a status
I
Positive
signal is output from the SO pin on the falling edges of the
SCK clock pulses.
When this pin is at a “H” level, SI input data is shifted into the
LSI on the falling edges of the SCK clock pulses and a status
signal is output from the SO pin on the rising edges of the
SCK clock pulses.
Channel status output pin.
O Positive Outputs the BUSYB or NCR signal for each channel by
inputting the OUTSTAT command.
Error output pin.
O Positive
Outputs a “H” level if an error occurs.
Chip select pin.
A “L” level on this pin accepts the SCK or SI inputs. When
I Negative
this pin is at a “H” level, neither the SCK nor SI signal is input
to the LSI.
I
Positive Synchronous serial clock input pin.
Synchronous serial data input pin.
When the DIPH pin is at a “L” level, data is shifted in on the
I
—
rising edges of the SCK clock pulses.
When the DIPH pin is at a “H” level, data is shifted in on the
falling edges of the SCK clock pulses.
Channel status serial output pin.
Outputs a status signal on the falling edges of the SCK clock
pulses when the DIPH pin is at a ”L” level; outputs a status
signal on the rising edges of the SCK clock pulses when the
O Positive
DIPH pin is at a ”H” level.
When the CSB pin is at a ”L” level, the status of each channel
is output serially in sync with the SCK clock. When the CSB
pin is at a ”H” level, this pin goes into a high impedance state.
Initial
value
0
0
analog
0
power
gnd
power
—
—
0
digital
0
digital
digital
1
0
digital
clk
1
0
digital
0
digital
Hi-Z
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嵌入式系统