FEDL610Q482P-0１
Issue Date: Dec.9, 2009
ML610Q482P
8-bit Microcontroller
GENERAL DESCRIPTION
This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port,
UART, I
2
C bus interface (master), buzzer driver, battery level detect circuit, and RC oscillation type A/D converter, are
incorporated around 8-bit CPU nX-U8/100.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture
parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation
(read operation) equivalent to mask ROM and is most suitable for battery-driven applications.
The on-chip debug function that is installed enables program debugging and programming.
FEATURES
CPU
8-bit RISC CPU (CPU name: nX-U8/100)
Instruction system: 16-bit instructions
Instruction set:
Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
On-Chip debug function
Minimum instruction execution time
30.5
s
(@32.768 kHz system clock)
0.244s (@4.096 MHz system clock)
Internal memory
Internal 64KByte Flash ROM (32K16 bits) (including unusable 1KByte TEST area)
Internal 4KByte Data RAM (40968 bits)
Interrupt controller
2 non-maskable interrupt sources (Internal source: 1, External source: 1)
18 maskable interrupt sources (Internal sources: 14, External sources: 4)
Time base counter
Low-speed time base counter
1
channel
Frequency compensation (Compensation range: Approx.
488ppm
to +488ppm. Compensation accuracy: Approx.
0.48ppm)
High-speed time base counter
1
channel
Watchdog timer
Non-maskable interrupt and reset
Free running
Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s @32.768 kHz)
Timers
8 bits
4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3)
Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3)
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FEDL610Q482P-01
LAPIS Semiconductor
ML610Q482P
PWM
Resolution 16 bits
1 channel
Synchronous serial port
Master/slave selectable
LSB first/MSB first selectable
8-bit length/16-bit length selectable
UART
TXD/RXD
1 channel
Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
Positive logic/negative logic selectable
Built-in baud rate generator
I
2
C bus interface
Master function only
Fast mode (400 kbps@4MH½), standard mode (100 kbps@1MH½, 50kbps@500kHz)
Buzzer driver
4 output modes, 8 frequencies, 16 duty levels
RC oscillation type A/D converter
24-bit counter
Time division
2 channels
Analog Comparator
Operating voltage:
V
DD
=1.8V½3.6V
Common mode input voltage:
0.2V½VDD－1.0V
Input offset voltage:
50mV(max)
Interrupt allow edge selection and sampling selection
General-purpose ports
Non-maskable interrupt input port
1 channel
Input-only port
6 channels (including secondary functions)
Output-only port
4 channels (including secondary functions)
Input/output port
22 channels (including secondary functions)
Reset
Reset through the RESET_N pin
Power-on reset generation when powered on
Reset when oscillation stop of the low-speed clock is detected
Reset by the watchdog timer (WDT) overflow
Power supply voltage detect function
Judgment voltages:
One of 16 levels
Judgment accuracy:
2%
(Typ.)
Clock
Low-speed clock: (This LSI can not guarantee the operation withou½ low-speed clock)
Crystal oscillation (32.768 kHz/38.4KHz)
High-speed clock:
Built-in RC oscillation (500 kHz)
Built-in PLL oscillation (8.192 MHz
2.5%),
crystal/ceramic oscillation (4.096 MHz), external clock
Selection of high-speed clock mode by software:
Built-in RC oscillation, built-in PLL oscillation, crystal/ceramic oscillation, external clock
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FEDL610Q482P-01
LAPIS Semiconductor
ML610Q482P
Power management
HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation
clock)
Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals.
Shipment
Chip
ML610Q482P-xxxWA (Blank product: ML610Q482P-NNNWA)
48-pin plastic TQFP
ML610Q482P-xxxTBZ03A (Blank product: ML610Q482P-NNNTBZ03A)
xxx: ROM code number
Guaranteed operating range
Operating temperature:
40C
to +85C
Operating voltage: V
DD
= 1.1V to 3.6V
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FEDL610Q482P-01
LAPIS Semiconductor
ML610Q482P
BLOCK DIAGRAM
ML610Q482P Block Diagram
Figure 1 show the block diagram of the ML610Q482P.
"*" indicates the secondary function of each port.
CPU (nX-U8/100)
EPSW1½3
PSW
Timing
Controller
GREG
0½15
ALU
Instruction
Decoder
ELR1½3
LR
EA
SP
Instruction
Register
Data-bus
RAM
4096byte
Interrupt
Controller
INT
1
INT
4
Power
INT
1
INT
4
INT
1
UART
INT
1
I
2
C
TBC
INT
1
PWM
8bit Timer
×4
Buzzer
INT
9
BZ0*
PWM0*
SDA*
SCL*
RXD0*
TXD0*
BUS
Controller
ECSR1½3
DSR/CSR
PC
Program
Memory
(Flash)
64Kbyte
V
PP
On-Chip
ICE
V
DD
V
SS
RESET_N
TEST
XT0
XT1
OSC0*
OSC1*
LSCLK*
OUTCLK*
V
DDL
V
DDX
OSC
RESET &
TEST
INT
1
SSIO
SCK0*
SIN0*
SOUT0*
WDT
IN0*
CS0*
RS0*
RT0*
CRT0*
RCM*
IN1*
CS1*
RS1*
RT1*
RC-ADC
×2
BLD
NMI
P00 to P03
P10, P11
GPIO
P20, P21, P22, P24
P30 to P35
P40 to P47
PA0 to PA7
CMPP
CMPM
Analog
Comparator
INT
1
Figure 1 ML610Q482P Block Diagram
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FEDL610Q482P-01
LAPIS Semiconductor
ML610Q482P
PIN CONFIGURATION
ML610Q482P TQFP48 Pin Layout
P30
P31
P34
P32
P33
P35
VDD
VDDL
VSS
VDDX
XT0
XT1
37
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
P22
P21
P20
VSS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
VDD
P11/OSC1
P10/OSC0
VSS
VPP
NMI
RESET_N
TEST
P47
P46
P45
P44
Note:
The assignment of the pads P30 to P35 are not in order.
Figure 2 ML610Q482P TQFP48 Pin Configuration
CMPP
CMPM
P00
P01
P02
P03
VSS
P24
P40
P41
P42
P43
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