FEDL62Q1500-02
Issue Date: Jan 9, 2019
ML62Q1500 Group
16-bit micro controller
GENERAL DESCRIPTION
ML62Q1500 Group is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and
integrated with program memory(Flash memory*), data memory(RAM), data Flash* and rich peripheral functions such as the
multiplier/divider, CRC operator, DMA controller, clock generator, Simplified RTC, timer, UART, synchronous serial port, I
2
C
bus interface unit, buzzer, Voltage Level Supervisor(VLS), successive approximation type A/D converter, D/A converter , analog
comparator, safety function and etc.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by pipeline architecture parallel
processing.
The built-in on-chip debug function enables debugging and programming the software. Also, ISP(In-System Programming)
function supports the Flash programming in production line.
The ML62Q1500 Group has five packages (48pin - 100pin) and ten kinds of memory sizes(32Kbyte - 512Kbyte).
Table 1 ML62Q1500 Group Product List
Program
memory
512Kbyte
384Kbyte
256Kbyte
192Kbyte
160Kbyte
128Kbyte
96Kbyte
64Kbyte
48Kbyte
32Kbyte
8Kbyte
16Kbyte
8Kbyte
16Kbyte
8Kbyte
4Kbyte
16Kbyte
Data memory
(RAM)
32Kbyte
Data Flash
48pin
TQFP48
−
−
−
−
−
−
ML62Q1534
−
ML62Q1533
ML62Q1532
ML62Q1531
ML62Q1530
52pin
TQFP52
−
−
−
−
−
−
ML62Q1544
−
ML62Q1543
ML62Q1542
ML62Q1541
ML62Q1540
64pin
QFP64
TQFP64
80pin
QFP80
100pin
QFP100
TQFP100
8Kbyte
ML62Q1559** ML62Q1569** ML62Q1579**
ML62Q1558** ML62Q1568** ML62Q1578**
ML62Q1557
ML62Q1556
ML62Q1555
−
ML62Q1554
−
ML62Q1553
ML62Q1552
ML62Q1551
ML62Q1550
ML62Q1567
ML62Q1566
ML62Q1565
ML62Q1564
−
ML62Q1563
−
−
−
−
ML62Q1577
ML62Q1576
ML62Q1575
ML62Q1574
−
ML62Q1573
−
−
−
−
**: These products are under developing and the electrical characteristics have not been fixed.
FEATURES
·
CPU
-
16-bit RISC CPU : nX-U16/100(A35 core)
-
Instruction system: 16-bit length instruction
‒ Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
‒ On-chip debug function built-in (supported by LAPIS on-chip debug emulator EASE1000)
‒ ISP (In-System Programming) function built-in
‒ Minimum instruction execution time
30.5 μs (at 32.768 kHz system clock)
62.5ns/41.6ns (at 16 MHz/24MHz system clock)
*:
This product uses Super Flash® technology licensed from Silicon Storage Technology, Inc. Super Flash®
is a registered trademark of Silicon Storage Technology, Inc.
1/67
FEDL62Q1500-02
·
Coprocessor for multiplication and division
-
Multiplication: 16bit × 16bit (operation time 4 cycles)
− Division: 32bit / 16bit (operation time 8 cycles)
− Division: 32bit / 32bit (operation time 16 cycles)
− Multiply-accumulate (non-saturating): 16bit × 16bit + 32bit (operation time 4 cycles)
− Multiply-accumulate (saturating): 16bit × 16bit + 32bit (operation time 4 cycles)
·
Operating voltage and temperature
‒ Operating voltage: V
DD
= 1.6 to 5.5 V
（Need
1.8V or higher at the power on）
‒ Operating temperature: -40 to +105 °C
·
Internal memory
‒ Prrogram Flash memory area
Rewrite count: 100 cycles
Rewrite unit: 32bit(4byte)
Erase unit: 16Kbyte/1Kbyte
Erase/Rewrite temperature: 0°C to +40°C
‒ Data Flash memory area
Rewrite count 10,000 cycles
Rewrite unit: 8bit(1byte)
Erase unit: all area/128byte
Erase/Rewrite temperature: -40°C to +85°C
Back Ground Operation(BGO) : CPU can work while erasing and rewriting.
‒ Data RAM area
Rewrite unit: 8bit/16bit(1byte/2byte)
Parity check function (Parity error reset or interrupt is generatable)
·
Clock
‒ Low-speed clock
Internal low-speed RC oscillation: Approx.32.768 kHz
External low-speed crystal oscillation: 32.768 kHz crystal resonator is connectable
3 modes is available for the crystal oscillatiion
×
Tough mode: Largest oscillation allowance to make highest resistance against leakage between the pins
×
Standard mode: Standard oscillation allowance and current consumption
×
Low power current mode: Smaller oscillation allowance than standard mode to make lower current consumption
‒ High-speed clock
PLL oscillation: 24MHz/16MHz is selectable by code option
‒ WDT(Watch Dog Timer) clock
Internal low-speed RC oscillation: Aprox. 1kHz
The WDT independent clock or the divided clock of internal low-speed clock is selectable by the code option.
·
Reset
‒ RESET_N pin reset
‒ Reset by power-on detection
‒ Reset by the watchdog timer (WDT) overflow
‒ Reset by WDT counter clear during the clear invalid period
‒ Reset by RAM parity error
‒ Reset by unused ROM access
‒ Reset by voltage level detection (VLS)
‒ The software reset by BRK instruction (reset CPU only)
‒ Reset to the peripheral circuits by Block Reset Control Registers (BRECON 0 to 3)
‒ One-time reset to the all peripheral circuits by Software Reset Control Register (SOFTRCON)
2/67
FEDL62Q1500-02
·
Power management
‒ HALT mode: CPU stops executing instruction, clock oscillations and peripheral circuits remain previous states
‒ HALT-H mode: CPU stops executing instruction, high-speed clock oscillation stops and peripheral circuits working with
low-speed clock remain previous states
‒ STOP mode: CPU stops executing instruction, both high-speed oscillation and low-speed oscillation stop.
‒ STOP-D mode: CPU stops executing instruction, both high-speed oscillation and low-speed oscillation stop. The internal
regulator’s output voltage (V
DDL
) goes down to reduce the current consumption.
‒ Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8, 1/16 or 1/32 of the
oscillation clock)
‒ Block Control Function: Powers down the circuits of unused function blocks (reset the block or stop supplying the clock)
·
Interrupt controller
-
Non-maskable interrupt source: 1 (Internal sources: WDT)
-
Maskable interrupt sources: max.51 (Internal sources: max.42, External sources: 9)
-
Four step interrupt levels
-
External interrupt ports : max 12
·
Watchdog timer(WDT)
‒ Operating clock is selectable (1kHz WDT independent clock or divided clock of internal 32.768kHz RC oscillation)
‒ Overflow period: 8 types selectable (7.8ms, 15.6ms, 31.3ms, 62.5ms, 125ms, 500ms, 2000ms and 8000ms@32.768kHz)
‒ Enabling or disabling the window function is selectable (The clear enable period is 50% or 75% of overflow period)
‒ WDT operation is selectable by code option (Enable or Disable)
‒ Readable WDT counter (WDT counter monitor function)
‒ The first overflow generates the WDT interrupt, and the second overflow generates the WDT reset when the counter clear
enable period is 100% of overflow period.
‒ The first overflow generates the WDT reset when the counter clear enable period is 50% or 75% of overflow period.
‒ The invalid clear reset generated when the WDT counter is cleared out of the WDT counter clear enable period.
·
DMA(Direct Memory Access) controller
-
Channel : 2ch
-
Transfer unit: 8bit/16bit
-
Max. transfer count: 1024 time
-
Transfer type: 2 cycle transfer
-
Transfer mode: Single transfer mode
Fixed address, address increments and address decrements
-
Transfer target: SFR/RAM
ßà
SFR/RAM (Transfer from/to Flash is not supported)
-
Transfer request: Serial unit interrupt, A/D interrupt, 16bit timer interrupt, Functional timer interrupt and External
interrupt.
·
Low-speed Time base counter
-
Devide the Low-speed clock(LSCLK) and generate 128Hz~1Hz internal pulse signals
-
Priodical interrupt
´
3 selectable from 8 frequencies (128Hz, 64Hz, 32Hz, 16Hz, 8Hz, 4Hz, 2Hz and 1Hz)
-
The time base clock output (1Hz or 2Hz) from general purpose ports (TBCOUT1).
-
Built-in frequency adjustment function
(adjustment range: approx.-488ppm ~ +488ppm, adjustment resolution: approx.0.119ppm)
·
Simplified RTC
-
Channel: 1 ch
-
Count by one second from “00 min. 00 sec” to “59 min. 59 sec”
-
One interrupt occurrence is selectable from four periodical interrupt requests (0.5sec, 1sec, 30sec or 60sec)
-
Protect function for incorrect writing the minutes and second.
3/67
FEDL62Q1500-02
·
Functional timer(FTM)
-
Channel: Max. 8ch
-
Repeat mode, Oneshot mode, Caputure mode, PWM mode1 and PWM mode 2(complementary output)
-
Same start/stop is avaible with different channels
(This function is not avaible with 16bit Genral Timer)
-
Event trigger (external interrupts, analog comprator interrupts, 16bit genral timer interrupts and Functional timer
interrupts)
-
Dead time is generatable.
-
Available to specify devision ratio of counter clock channel by channel
·
16bit General timers
-
Channel: Max. 8ch
‒ 8 bits timer mode and 16-bit timer mode (1ch 16-bit timer is configurable as 2ch 8-bit timer)
-
Same start/stop is avaible with different channels
(This function is not avaible with Functional Timer)
‒ Timer output (toggled by overflow)
-
Available to specify devision ratio of counter clock channel by channel
·
Serial communication unit
-
Channel: Max. 6ch
-
Synchronous Serial Port or UART is seletable in each channel
< Synchronous Serial Port >
‒ Master/slave selectable
‒ LSB first/MSB first selectable
‒ 8-bit length/16-bit length selectable
< UART >
‒ Full-duplex communication x 2 ch(One Full-duplex UART is configurable as two half-duplex UARTs)
‒ 5~8 bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
‒ Positive logic/negative logic selectable
‒ LSB first/MSB first selectable
‒ Wide range of communication speed
32.768kHz operation clock : 1bps to 4,800bps
24MHz operation clock : 600bps to 3Mbps
16MHz operation clock : 300bps to 2Mbps
‒ Internal baud rate generator
·
I
2
C bus interface unit (Master/Slave)
‒ Channel: 1ch
‒ Master or Slave mode is selectable
< Master function >
‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)
‒ Handshake (Clock syncronization)
‒ 7bit address format (10bit address format is supported)
< Slave function >
‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)
‒ Clock stretch function
‒ 7bit address format
·
I
2
C bus interface (Master only)
‒ Channel: 2ch
‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)
‒ Handshake (Clock syncronization)
‒ 7bit address format (10bit address format is supported)
4/67
FEDL62Q1500-02
·
General-purpose ports (GPIO)
‒ I/O port: Max. 92 (Including one pin for on-chip debug and pins for other shared functions)
‒ Input port: Max. 2(Including a shared function)
‒ External interrput function
´
12
‒ LED driver port : Max. 91
‒ Carrier frequency output function (used for IR communication)
·
Successive approximation type A/D converter
‒ Channel: Max.16ch
‒ Resolution: 10bit
‒ Conversion time: Selectable 2.25μs (min) /channel (When the conversion clock is 8MHz)
‒ V
DD
, Internal reference voltage(Approx. 1.55V) or Extenal reference voltage (V
REF
pin) is selectable.
‒ Scan function (repeat conversion)
‒ One result register for each channel
‒ Interrupt by threshold of conversion result
‒ Temprature sensor for low-speed RC oscillation adjustment
·
Voltage level superviosr (VLS)
‒ Accuracy: ±4%
‒ Threshold voltage: 12 values selectable (1.85V ~ 4.00V)
‒ Voltage level detection reset (VLS reset)
‒ Voltage level detection interrupt (VLS0 interrupt)
·
Analog comparator
‒ Channel: 2ch
‒ Interrupts allow edge selection and sampling selection
‒ An external or an internal reference voltage is selectable
·
D/A converter
‒ Channel: Max 2ch
‒ Resolution: 8bit
‒ Output impedance: 6k ohm(Typ.)
‒ R-2R radder method
·
Buzzer
‒ 4 buzzer mode (Repeat sound, Single sound, Intermittent sound 1 and Intermittent sound 2)
‒ 8frequencies (4.096kHz to 293Hz)
‒ 15 step duty (1/16 to 15/16)
‒ Slectable the logic of buzzer output pin (Possitive or Negative logic)
·
CRC(Cyclic Redundancy Check) operation function
‒ Generation eqution: X
16
+X
12
+X
5
+1
‒ LSB first or MSB first is selectable
‒ Automatic CRC mode: Automatic CRC calculation with data of program memory in HALT mode
5/67
