FEDL67Q5250-03
Issue Date: Sep. 2, 2008
ML67Q5250
DFT Based Fingerprint Authentication LSI
GENERAL DESCRIPTION
The ML67Q5250 is a single chip LSI that executes fingerprint authentication without external memory by using
the embedded fingerprint authentication accelerator. This fingerprint authentication accelerator uses DFT(Discrete
Fourier Transform) based algorithm licensed from Precise Biometrics, and supports AuthenTec's slide sensors and
certain touch sensors from several sensor manufacturers. Besides the ML67Q5250 has the secure circuit to protect
enrolled fingerprint data from unauthorized access. Thus this LSI helps customers quickly design new products
that offer convenient security as far as high performance fingerprint authentication, low cost and high level of
security.
FEATURES
Fingerprint authentication
- DFT (Discrete Fourier Transform) based algorithm licensed from Precise Biometrics
This DFT based algorithm achieves a lower FTE (False To Enrollment rate) and a higher authentication
accuracy especially when a slide sensor is used, as compared to the minutiae algorithm.
- Easy-to-use
The fingerprint authentication is performaed by the fingerprint authentication accelerator, which does not ask
customers for so complicated control.
- No external memory
Customer’s application program and up to 15 fingerprint data can be stored in the embedded Flash memory on
the ML67Q5250. No external memory is required, when a slide sensor is used. External memory is required
when a touch sensor is used.
- High-speed authentication, besides low power consumption
The highly optimized fingerprint authentication accelerator achieves high-speed authentication using a low
speed clock.
Authentication : < 0.8 seconds (1:1 authentication)
< 1.8 seconds (1:15 authentication)
Enrollment
: < 2 seconds/finger
- Applicable fingerprint sensor
Slide sensor
: AuthenTec AES1510 (128
8 pixels)
AuthenTec AES2510 (192
16 pixels)
Touch sensor : Any vendor’s touch sensor as far as 256
360 pixels max., 8 bits/pixel and 5008 dpi
CPU
- 32-bit RISC CPU (ARM7TDMI)
- Little endian format
- Instruction system: A high-density 32-bit instruction and a 16-bit instruction of high-object efficiency, which is
the subset of the 32-bit instruction, can be executed in mixed mode.
- General-purpose register: 32 bits x 31 registers
- Built-in barrel shifter (ALU and barrel shift operation can be executed by one instruction)
- Built-in debugging function (JTAG interface)
The JTAG interface pin is shared with GPIO.
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FEDL67Q5250-03
LAPIS Semiconductor
ML67Q5250
Internal RAM
- Working RAM for CPU
: 16 Kbytes
Internal Flash ROM
- 128 Kbyte Flash ROM
- Program ROM
: 64 Kbytes
This program ROM includes drivers for fingerprint authentication and peripherals.
Erase/rewrite times : 100 max.
- Data ROM for storing fingerprint data : 64 Kbytes
Erase/rewrite times : 10,000 max. (when enrolling one fingerprint data)
External memory controller
- ROM/Flash
• 1 bank x 4 Mbytes
• Supports 16-bit devices
• Bootable from external ROM/Flash
This function can not be used during security function being activated.
- SRAM
• 1 bank
4 Mbytes
• Supports 16-bit devices
- External I/O
• 2-bank
4 Mbytes
• Supports 8-bit/16-bit devices
• Enable to set address setup, RW/WE pulse, and data off timing in system clock cycle unit
• Supports an access wait function by wait signal
Interrupt control
- FIQ: 1 interrupt source
- IRQ: 22 interrupt sources
7 priority levels can be set for each source.
DMA controller (DMAC)
- 2 channels
- Enable to allocate multiple DMA transfer request sources for each channel.
- Channel priority: fixed mode/round robin mode
- DMA transfer mode: cycle steal mode/burst mode
- DMA request type: software requests/hardware requests
- Maximum transfer count : 65,536
- Data transfer size: 8 bits/16 bits/32 bits
- Transfer request source: CPU, SPI, Synchronous SIO, Smartcard IF
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FEDL67Q5250-03
LAPIS Semiconductor
ML67Q5250
GPIO
- 13 bits
1 channel, 14 bits
1 channel, and 16 bits
1 channel
- Enable to setting input mode or output mode for each bit
- Enable to setting as interruption source for each bit
- Interruption mode: level/edge and positive logic/negative logic
System timer
- 16-bit auto reload timer
1 channel
Flexible timer (FTM)
- 16-bit timer
3 channels
- Operating mode
Auto reload timer (ART) /Compare Out (CMO) /pulse width modulation (PWM) /capture (CAP) mode.
Watch dog timer (WDT)
- 16-bits timer
- 8.389 seconds max. (when CPU operating frequency is 32 MHz)
- Enables generation of interrupt or reset by setting
SIO (UART)
- Full-duplex asynchronous mode
- Built-in baud rate generator
SPI
- 2 channels of full-duplex serial peripheral interfaces
- Operating mode: master mode/slave mode
- Data transfer size: 8 bits (byte) / 16 bits (word)
- Built-in 16-byte/16-word FIFO on the transmission side and the reception side
- Supports DMA transfer (master/slave mode)
Synchronous SIO (SSIO)
- 8-bit clock synchronous serial port
1 channel
- Selectable clock polarity
- Selectable LSB first or MSB first
- Operation mode: master mode/slave mode
- Supports DMAC transfer (in master mode only)
Smart Card interface (Smartcard IF)
- ISO UART
1 channel
- Built-in 16-byte FIFO
- Built-in parity error counter in receive mode and transmit mode at automatic retransmission
- Supports asynchronous protocol of T = 0 and T = 1 according to ISO7816 and EMV
- Built-in error detection code generation and error detection functions by hardware
- Supports DMA transfer
USB2.0 full-speed device
- Compliant with Universal Serial Bus (USB) 2.0
- Full speed (12 Mbps)
1 port.
- End points: 5 or 6
- Supports all data transfer types (control transfer, bulk transfer, interrupt transfer, isochronous transfer).
- Built-in SOF generation and CRC5/16 generation functions
- Access size to data transfer FIFOs: 8 bits/16 bits/32 bits
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FEDL67Q5250-03
LAPIS Semiconductor
ML67Q5250
Random number generator (RANDOM)
- Generates 8-bit random numbers
Clock
- Input clock: 12 MHz (oscillator connected)
- System clock (CPU operating clock): 32 MHz
System clock is generated by PLL using 12MHz clock.
- Output clock: 6/12 MHz for fingerprint sensor
Power management
- Power saving mode
• Individual module clock stop mode:
Clock operation/stop can be set for each functional block.
• Sensor interrupt wait mode:
Start /stop of finger sensor clock output and internal PLL are selectable.
• STOP mode:
Start /stop of internal PLL and OSC oscillator circuit are selectable.
Package
- 144-pin LFBGA (P-LFBGA144-1111-0.80)
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FEDL67Q5250-03
LAPIS Semiconductor
ML67Q5250
BLOCK DIAGRAM
Figure 1 shows a block diagram of this LSI.
JTAG
ARM7TDMI
rev.3
Embedded
Flash ROM
128 KB
Fingerprint Accelerator
Interrupt
Control
RAM
16KB
DMAC
2ch
Memory
Controller
Peripherals
PLL
System
Timer
SIO
USB
FS
Device
GPIO
3 ch
(43 bits)
Smart
Card IF
1ch
SPI
2ch
FTM
3ch
WDT
SSIO
1ch
RAN
DOM
Figure 1 Block Diagram
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