This 8-bit TRI-STATE shift storage register utilizes advanced
silicon-gate CMOS technology Along with the low power
consumption and high noise immunity of standard CMOS
integrated circuits it has the ability to drive 15 LS-TTL
loads This circuit also features operating speeds compara-
ble to the equivalent low power Schottky device
The MM54HC299 MM74HC299 features multiplexed in-
puts outputs to achieve full 8-bit data handling in a single
20-pin package Due to the large output drive capability and
TRI-STATE feature this device is ideally suited for interfac-
ing with bus lines in a bus oriented system
Two function select inputs and two output control inputs are
used to choose the mode of operation as listed in the func-
tion table Synchronous parallel loading is accomplished by
taking both function select lines S0 and S1 high This places
the TRI-STATE outputs in a high impedance state which
permits data applied to the input output lines to be clocked
into the register Reading out of the register can be done
while the outputs are enabled in any mode A direct overrid-
ing CLEAR input is provided to clear the register whether
the outputs are enabled or disabled
The 54HC 74HC logic family is functionally as well as pinout
compatible with the standard 54LS 74LS logic family All
inputs are protected from damage due to static discharge by
internal diode clamps to V
CC
and ground
Features
Y
Y
Y
Y
Y
Typical operating frequency 40 MHz
Typical propagation delay 20 ns
Low quiescent current 80
mA
maximum (74HC)
High output drive for bus applications
Low quiescent current 1
mA
maximum
Connection Diagram
Dual-In-Line Package
TL F 5207 – 1
Order Number MM54HC299 or MM74HC299
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 5207
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Notes 1
2)
Operating Conditions
Min
Supply Voltage V
CC
DC Input or Output Voltage
V
IN
V
OUT
Operating Temp Range (T
A
)
MM HC
MM HC
Input Rise or Fall Times
V
CC
e
V
t
r
t
f
V
CC
e
V
V
CC
e
V
b
b
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
CD
)
DC Output Current per pin (I
OUT
)
b
0 5 to
a
7 0V
b
1 5 to V
CC
a
1 5V
b
0 5 to V
CC
a
0 5V
g
20 mA
g
25 mA (Q
A’
Q
H’
)
g
35 mA (others)
Max
V
CC
Units
V
V
a
a
C
C
ns
ns
ns
g
70 mA
DC V
CC
or GND Current per pin (I
CC
)
b
65 C to
a
150 C
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
600 mW
S O Package only
500 mW
Lead Temp (T
L
) (Soldering 10 seconds)
260 C
DC Electrical Characteristics
(Note 4)
Symbol
V
IH
Parameter
Minimum High Level Input
Voltage
Maximum Low Level Input
Voltage
Minimum High Level
Output Voltage
V
IN
e
V
IH
or V
IL
l
I
OUT
l
s
mA
Conditions
V
CC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
g
g
g
g
g
g
T
A
e
25 C
Typ
74HC
T
A
eb
40 to 85 C
54HC
T
A
eb
55 to 125 C
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
Guaranteed Limits
V
IL
V
OH
Q
A
Q
H
Outputs
V
IN
e
V
IH
or V
IL
l
I
OUT
l
s
mA
l
I
OUT
l
s
mA
V
IN
e
V
IH
or V
IL
l
I
OUT
l
s
mA
l
I
OUT
l
s
mA
V
IN
e
V
IH
or V
IL
l
I
OUT
l
s
mA
A Q
A
thru H Q
H
Outputs
V
OL
Maximum Low Level
Output Voltage
Q
A
and Q
H
Outputs
V
IN
e
V
IH
or V
IL
l
I
OUT
l
s
mA
l
I
OUT
l
s
mA
V
IN
e
V
IH
or V
IL
l
I
OUT
l
s
mA
l
I
OUT
l
s
mA
V
IN
e
V
CC
or GND
V
OUT
e
V
CC
or
GND
G
e
V
IH
V
IN
e
V
CC
or GND
I
OUT
e
mA
A Q
A
thru H Q
H
Outputs
I
IN
I
OZ
Maximum Input Current
Maximum TRI STATE Output
Leakage Currrent
I
CC
Maximum Quiescent Supply
Current
V
mA
Note 1
Absolute Maximum Ratings are those values beyond which damage to the device may occur
Note 2
Unless otherwise specified all voltages are referenced to ground
Note 3
Power Dissipation temperature derating
plastic ‘‘N’’ package
b
12 mW C from 65 C to 85 C ceramic ‘‘J’’ package
b
12 mW C from 100 C to 125 C
Note 4
For a power supply of 5V
g
10% the worst-case output voltages (V
OH
and V
OL
) occur for HC at 4 5V Thus the 4 5V values should be used when
designing with this supply Worst-case V
IH
and V
IL
occur at V
CC
e
5 5V and 4 5V respectively (The V
IH
value at 5 5V is 3 85V ) The worst-case leakage current (I
IN
I
CC
and I
OZ
) occur for CMOS at the higher voltage and so the 6 0V values should be used
V
IL
limits are currently tested at 20% of V
CC
The above V
IL
specification (30% of V
CC
) will be implemented no later than Q1 CY’89
2
AC Electrical Characteristics
V
CC
e
5V
Symbol
f
MAX
t
PHL
t
PLH
t
PHL
t
PHL
t
PLH
t
PHL
t
PZL
t
PZH
t
PHZ
t
PLZ
t
S
Parameter
Maximum Operating
Frequency
Maximum Propagation
Delay Clock to Q
A
or Q
H
Maximum Propagation
Delay Clear to Q
A
or Q
H
Maximum Propagation
Delay Clock to Q
A
Q
H
Maximum Propagation
Delay Clear to Q
A
Q
H
Maximum Enable Time
Maximum Disable Time
Minimum Setup
Time
Minimum Hold
Time
Minimum Pulse Width
Clear Removal Time
Select
Data
Select
Data
C
L
e
C
L
e
T
A
e
25 C t
r
e
t
f
e
6 ns C
L
e
45 pF
Typ
Guaranteed
Limit
Units
MHz
ns
ns
pF
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
C
L
e
pF
R
L
e
kX
C
L
e
pF
R
L
e
kX
t
H
t
W
t
REM
AC Electrical Characteristics
C
L
e
50 pF
Symbol
Parameter
Conditions
t
r
e
t
f
e
6 ns unless otherwise specified
T
A
e
25 C
Typ
74HC
T
A
eb
40 to 85 C
54HC
T
A
eb
55 to 125 C
V
CC
V
V
V
V
V
V
V
V
V
Units
Guaranteed Limits
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
MAX
Maximum Operating Frequency
t
PHL
t
PLH
Maximum Propagation
Delay Clock to Q
A
or Q
H
Maximum Propagation
Delay Clear to Q
A
or Q
H
Maximum Propagation
Delay Clock to Q
A
Q
H
C
L
e
C
L
e
C
L
e
C
L
e
C
L
e
C
L
e
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
t
PHL
t
PHL
t
PLH
V
V
V
V
V
V
V
V
V
V
V
V
3
t
PHL
Maximum Propagation
Delay Clear to Q
A
Q
H
C
L
e
C
L
e
C
L
e
C
L
e
C
L
e
C
L
e
AC Electrical Characteristic
(Continued) C
L
e
50 pF
Symbol
Parameter
Conditions
R
L
e
1 kX
C
L
e
50 pF
C
L
e
150 pF
C
L
e
50 pF
C
L
e
150 pF
C
L
e
50 pF
C
L
e
150 pF
t
PHZ
t
PLZ
Maximum Output Disable Time R
L
e
1 kX
C
L
e
50 pF
t
S
Minimum Setup Time
Data Select S
L
or S
R
Minimum Hold Time
Data Select S
L
or S
R
Minimum Clear Removal Time
2 0V
2 0V
4 5V
4 5V
6 0V
6 0V
2 0V
4 5V
6 0V
2 0V
4 5V
6 0V
2 0V
4 5V
6 0V
2 0V
4 5V
6 0V
2 0V
4 5V
6 0V
2 0V
4 5V
6 0V
2 0V
4 5V
6 0V
Outputs Enabled
Outputs Disabled
240
110
5
15
70
90
22
30
19
24
70
22
19
V
CC
Typ
t
PZH
t
PZL
Maximum Output Enable
t
r
e
t
f
e
6 ns unless otherwise specified
74HC
54HC
T
A
eb
40 to 85 C T
A
eb
55 to 125 C Units
Guaranteed Limits
200
275
40
55
34
47
200
40
34
125
25
21
0
0
0
10
10
10
125
25
21
1000
500
400
75
15
13
225
310
45
62
38
51
225
45
38
140
28
25
0
0
0
10
10
10
140
28
25
100
500
400
90
18
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
10
20
10
20
10
20
pF
pF
T
A
e
25 C
160
220
32
44
28
47
160
32
28
100
20
17
0
0
0
10
10
10
100
20
17
1000
500
400
60
12
10
t
H
t
REM
t
W
Minimum Pulse Width
Clock and Clear
Maximum Input Rise
and Fall Time
t
r
t
f
t
THL
t
TLH
Maximum Output Rise
and Fall Time Clock
C
PD
C
IN
C
OUT
Power Dissipation
Capacitance
Maximum Input Capacitance
Capacitance
Maximum TRI-STATE
Output Capacitance
Note 5
C
PD
determines the no load dynamic power consumption P
D
e
C
PD
V
CC2
f
a
I
CC
V
CC
and the no load dynamic current consumption
I
S
e
C
PD
V
CC
f
a
I
CC
Function Table
Inputs
Mode
Clear
L
L
H
H
H
H
H
H
H
Function
Select
S1
Clear
Hold
Shift Right
Shift Left
Load
X
L
L
X
L
L
H
H
H
L
X
L
X
H
H
L
L
H
Output
Control
G2
L
L
L
L
L
L
L
L
X
X
X
X
L or H
L
L
L
L
L
L
L
L
X
Inputs Outputs
Outputs
Clock Serial A Q
A
B Q
B
C Q
C
D Q
D
E Q
E
F Q
F
G Q
G
H Q
H
Q
A’
Q
H’
SL SR
X
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
X
X
L
L
Q
A0
Q
A0
H
L
Q
Bn
Q
Bn
a
L
L
Q
B0
Q
B0
Q
An
Q
An
Q
Cn
Q
Cn
b
L
L
Q
C0
Q
C0
Q
Bn
Q
Bn
Q
Dn
Q
Dn
c
L
L
Q
D0
Q
D0
Q
Cn
Q
Cn
Q
En
Q
En
d
L
L
Q
E0
Q
E0
Q
Dn
Q
Dn
Q
Fn
Q
Fn
e
L
L
Q
F0
Q
F0
Q
En
Q
En
Q
Gn
Q
Gn
f
L
L
Q
G0
Q
G0
Q
Fn
Q
Fn
Q
Hn
Q
Hn
g
L
L
L
L
L
L
S0 G1
Q
H0
Q
A0
Q
H0
Q
H0
Q
A0
Q
H0
Q
Gn
Q
Gn
H
L
h
H
L
Q
Bn
Q
Bn
a
Q
GN
Q
GN
H
L
h
u
u
u
u
u
When one or both controls are high the eight input output terminals are disabled to the high-impedance state however sequential operation or clearing of
