Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC8315EEC
Rev. 2, 11/2011
MPC8315E
PowerQUICC II Pro Processor
Hardware Specifications
This document provides an overview of the MPC8315E
PowerQUICC™ II Pro processor features, including a block
diagram showing the major functional components. The
MPC8315E contains a core built on Power Architecture™
technology. It is a cost-effective, low-power, highly
integrated host processor that addresses the requirements of
several storage, consumer, and industrial applications,
including main CPUs and I/O processors in network attached
storage (NAS), voice over IP (VoIP) router/gateway,
intelligent wireless LAN (WLAN), set top boxes, industrial
controllers, and wireless access points. The MPC8315E
extends the PowerQUICC II Pro family, adding higher CPU
performance, new functionality, and faster interfaces while
addressing the requirements related to time-to-market, price,
power consumption, and package size. Note that while the
MPC8315E supports a security engine, the MPC8315 does
not.
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
MPC8315E Features . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 17
DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 18
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Ethernet: Three-Speed Ethernet, MII Management . 24
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 51
PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
TDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 76
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
System Design Information . . . . . . . . . . . . . . . . . . 100
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 103
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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© Freescale Semiconductor, Inc., 2011. All rights reserved.
Overview
1
Overview
The MPC8315E incorporates the e300c3 (MPC603e-based) core, which includes 16 Kbytes of L1
instruction and data caches, on-chip memory management units (MMUs), and floating-point support. In
addition to the e300 core, the SoC platform includes features such as dual enhanced three-speed 10, 100,
1000 Mbps Ethernet controllers (eTSECs) with SGMII support, a 32- or 16-bit DDR1/DDR2 SDRAM
memory controller, dual SATA 3 Gbps controllers (MPC8315E-specific), a security engine to accelerate
control and data plane security protocols, and a high degree of software compatibility with
previous-generation PowerQUICC processor-based designs for backward compatibility and easier
software migration. The MPC8315E also offers peripheral interfaces such as a 32-bit PCI interface with
up to 66 MHz operation, 16-bit enhanced local bus interface with up to 66 MHz operation, TDM interface,
and USB 2.0 with an on-chip USB 2.0 PHY.
The MPC8315E offers additional high-speed interconnect support with dual integrated SATA 3 Gbps
interfaces and dual single-lane PCI Express interfaces. When not used for PCI Express, the SerDes
interface may be configured to support SGMII. The MPC8315E security engine (SEC 3.3) allows
CPU-intensive cryptographic operations to be offloaded from the main CPU core. This figure shows a
block diagram of the MPC8315E.
MPC8315E
e300c3 Core with
Power Management
DUART
I
2
C
Timers
GPIO
16-KB
I-Cache
Interrupt
Controller
FPU
16-KB
D-Cache
TDM
Enhanced
Local Bus,
SPI
DDR1/DDR2
Controller
Security
Engine 3.3
I/O
Sequencer
(IOS)
PCI
Express
x1
PCI
Express
x1
USB 2.0 HS
Host/Device/OTG SATA
ULPI
On-Chip
HS PHY
PHY
SATA
PHY
eTSEC
eTSEC
RGMII, (R)MII
RTBI, SGMII
RGMII, (R)MII
RTBI, SGMII
PCI
DMA
Note:
The MPC8315 do not include a security engine.
Figure 1. MPC8315E Block Diagram
2
2.1
MPC8315E Features
e300 Core
The following features are supported in the MPC8315E.
The e300 core has the following features:
• Operates at up to 400 MHz
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
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MPC8315E Features
•
•
•
•
16-Kbyte instruction cache, 16-Kbyte data cache
One floating point unit and two integer units
Software-compatible with the Freescale processor families implementing the PowerPC
Architecture
Performance monitor
2.2
Serial Interfaces
The following interfaces are supported in the MPC8315E.
• Two enhanced TSECs (eTSECs)
• Two Ethernet interfaces using one RGMII/MII/RMII/RTBI or SGMII (no GMII)
• Dual UART, one I
2
C, and one SPI interface
2.3
Security Engine
The security engine is optimized to handle all the algorithms associated with IPSec, 802.11i, and iSCSI.
The security engine contains one crypto-channel, a controller, and a set of crypto execution units (EUs).
The execution units are:
• Public key execution unit (PKEU)
— RSA and Diffie-Hellman (to 4096 bits)
— Programmable field size up to 2048 bits
— Elliptic curve cryptography (1023 bits)
— F2m and F(p) modes
— Programmable field size up to 511 bits
• Data encryption standard execution unit (DEU)
— DES, 3DES
— Two key (K1, K2) or three key (K1, K2, K3)
— ECB, CBC, CFB-64 and OFB-64 modes for both DES and 3DES
• Advanced encryption standard unit (AESU)
— Implements the Rinjdael symmetric key cipher
— Key lengths of 128, 192, and 256 bits
— ECB, CBC, CCM, CTR, GCM, CMAC, OFB, CFB, XCBC-MAC and LRW modes
— XOR acceleration
• Message digest execution unit (MDEU)
— SHA with 160-bit, 256-bit, 384-bit and 512-bit message digest
— SHA-384/512
— MD5 with 128-bit message digest
— HMAC with either algorithm
• Random number generator (RNG)
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
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MPC8315E Features
•
— Combines a True Random Number Generator (TRNG) and a NIST-approved Pseudo-Random
Number Generator (PRNG) (as described in Annex C of FIPS140-2 and ANSI X9.62).
Cyclical Redundancy Check Hardware Accelerator (CRCA)
— Implements CRC32C as required for iSCSI header and payload checksums, CRC32 as required
for IEEE 802 packets, as well as for programmable 32 bit CRC polynomials
2.4
DDR Memory Controller
The DDR1/DDR2 memory controller includes the following features:
• Single 16- or 32-bit interface supporting both DDR1 and DDR2 SDRAM
• Support for up to 266 MHz data rate
• Support for two physical banks (chip selects), each bank independently addressable
• 64-Mbit to 2-Gbit (for DDR1) and to 4-Gbit (for DDR2) devices with x8/x16 data ports (no direct
x4 support)
• Support for one 16-bit device or two 8-bit devices on a 16-bit bus or two 16-bit devices on a 32-bit
bus
• Support for up to 16 simultaneous open pages
• Supports auto refresh
• On-the-fly power management using CKE
• 1.8-/2.5-V SSTL2 compatible I/O
2.5
PCI Controller
The PCI controller includes the following features:
• Designed to comply with
PCI Local Bus Specification Revision 2.3
• Single 32-bit data PCI interface operates at up to 66 MHz
• PCI 3.3-V compatible (not 5-V compatible)
• Support for host and agent modes
• On-chip arbitration, supporting three external masters on PCI
• Selectable hardware-enforced coherency
2.6
TDM Interface
The TDM interface includes the following features:
• Independent receive and transmit with dedicated data, clock and frame sync line
• Separate or shared RCK and TCK whose source can be either internal or external
• Glueless interface to E1/T1 frames and MVIP, SCAS, and H.110 buses
• Up to 128 time slots, where each slot can be programmed to be active or inactive
• 8- or 16-bit word widths
• The TDM Transmitter Sync Signal (TFS), Transmitter Clock Signal (TCK) and Receiver Clock
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
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MPC8315E Features
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Signal (RCK) can be configured as either input or output
Frame sync and data signals can be programmed to be sampled either on the rising edge or on the
falling edge of the clock
Frame sync can be programmed as active low or active high
Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame
MSB or LSB first support
2.7
USB Dual-Role Controller
The USB controller includes the following features:
• Designed to comply with
USB Specification, Rev. 2.0
• Supports operation as a stand-alone USB device
— Supports one upstream facing port
— Supports three programmable USB endpoints
• Supports operation as a stand-alone USB host controller
— Supports USB root hub with one downstream-facing port
— Enhanced host controller interface (EHCI) compatible
• Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation.
Low-speed operation is supported only in host mode.
• Supports UTMI+ low pin interface (ULPI) or on-chip USB-2.0 full-speed/high-speed PHY
• Supports USB on-the-go mode, which includes both device and host functionality, when using an
external ULPI PHY
2.8
Dual PCI Express Interfaces
The PCI Express interfaces have the following features:
• PCI Express 1.0a compatible
• x1 link width
• Selectable operation as root complex or endpoint
• Both 32- and 64-bit addressing
• 128-byte maximum payload size
• Support for MSI and INTx interrupt messages
• Virtual channel 0 only
• Selectable Traffic Class
• Full 64-bit decode with 32-bit wide windows
• Dedicated descriptor based DMA engine per interface with separate read and write channels
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
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5
嵌入式系统
