MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MPC903
1:6 PCI Clock Generator/
Fanout Buffer
The MPC903, MPC904 and MPC905 are six output clock generation
devices targeted to provide the clocks required in a 3.3V or 5.0V PCI
environment. The device operates from a 3.3V supply and can interface
to either a TTL input or an external crystal. The inputs to the device can be
driven with 5.0V when the VCC is at 3.3V. The outputs of the
MPC903/904/905 meet all of the specifications of the PCI standard. The
three devices are identical except in the function of the Output Enables.
MPC904
MPC905
1:6 PCI
CLOCK GENERATOR/
FANOUT BUFFER
•
•
•
•
•
•
Six Low Skew Outputs
Synchronous Output Enables for Power Management
Low Voltage Operation
XTAL Oscillator Interface
16-Lead SOIC Package
5.0V Tolerant Enable Inputs
16
1
The MPC903/904/905 device is targeted for PCI bus or processor bus
environments with up to 12 clock loads. Each of the six outputs on the
MPC903/904/905 can drive two series terminated 50Ω transmission
lines. This capability effectively makes the MPC903/904/905 a 1:12
fanout buffer.
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
The MPC903 offers two synchronous enable inputs to allow users
flexibility in developing power management features for their designs.
Both enable signals are active HIGH inputs. A logic ‘0’ on the Enable1
input will pull all of the outputs into the logic ‘0’ state and shut down the
internal oscillator for a zero power sleep state. A logic ‘0’ on the Enable2
input will disable only the BCLK5 output. The Enable2 input can be used to disable any high power device for system power
savings during periods of inactivity. Both enable inputs are synchronized internal to the chip so that the output disabling will
happen only when the outputs are already LOW. This feature guarantees no runt pulses will be generated during enabling and
disabling. Note that when the MPC903 is re-enabled via the Enable1 pin, the user must allow for the oscillator to regain stability.
Thus, the re-enabling of the chip cannot occur instantaneously. The MPC904 and MPC905 Enable functions are slightly different
than the 903 and are outlined in the function tables on the following page.
VDD (3)
GND (3)
Pinout: 16-Lead Plastic Package
(Top View)
BCLK0
XTAL_OUT 1
XTAL_IN
BCLK1
BCLK2
XTAL_OUT
BCLK3
BCLK4
SYNCHRONIZE
BCLK5
Enable2
SYNCHRONIZE
Enable2 2
GND1 3
BCLK0 4
VDD1 5
Enable1
BCLK1 6
GND2 7
BCLK2 8
16 XTAL_IN
15 Enable1
14 BCLK5
13 VDD3
12 BCLK4
11 GND3
10 BCLK3
9 VDD2
10/96
©
Motorola, Inc. 1996
1
REV 3
MPC903 MPC904 MPC905
FUNCTION TABLE
Outputs 0 to 4
ENABLE1
0
0
1
1
ENABLE2
0
1
0
1
MPC903
Low
Low
Toggling
Toggling
MPC904
Low
Low
Toggling
Toggling
MPC905
Low
Low
Toggling
Toggling
MPC903
Low
Low
Low
Toggling
Output 5
MPC904
Low
Toggling
Low
Toggling
MPC905
Low
Toggling
Low
Toggling
MPC903
OFF
OFF
ON
ON
OSC (On/Off)
MPC904
OFF
ON
ON
ON
MPC905
ON
ON
ON
ON
ABSOLUTE MAXIMUM RATINGS*
Symbol
VDD
VIN
Toper
Tstg
Tsol
Tj
P(E1=1)
P(E1=0)
ESD
ILatch
Supply Voltage
Input Voltage
Operating Temperature Range
Storage Temperature Range
Soldering Temperature Range (10 Sec)
Junction Temperature Range
Power Dissipation
Power Dissipation
Static Discharge Voltage
Latch Up Current
2000
50
Parameter
Min
–0.5
–0.5
0
–65
Max
4.6
VCC + 0.5
+70
+150
+260
+125
TBD
40
Unit
V
V
°C
°C
°C
°C
mW
µW
V
mA
* Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
TA
VDD
tDCin
Parameter
Ambient Temperature Range
Positive Supply Voltage (Functional Range)
Thigh (at XTAL_IN Input)
Tlow (at XTAL_IN Input)
Min
0
3.0
0.44T
1
0.44T
1
Max
70
3.6
0.56T
1
0.56T
1
Unit
°C
V
T = Period
1. When using External Source for reference, requirement to meet PCI clock duty cycle requirement on the output.
DC CHARACTERISTICS
(TA = 0–70°C; VDD = 3.3V
±0.3V)
Symbol
VIH
VIL
VOH
VOL
IIH
IIL
ICC
Characteristic
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input High Current
Input Low Current
Power Supply Current
DC
33MHz
66MHz
XTAL_IN
Others
20
37
78
2.4
0.4
2.5
2
2.5
45
95
9.0
4.5
Min
2.0
Typ
Max
5.5
2
0.8
Unit
V
V
V
V
µA
µA
µA
mA
mA
pF
IOH = –36mA
1
IOL = 36mA
1
Condition
CIN
Input Capacitance
1. The MPC903/904/905 outputs can drive series terminated or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge
(see Applications Info).
2. XTAL_IN input will sink up to 10mA when driven to 5.5V. There are no reliability concerns associated with the condition. Note that the Enable1
input must be a logic HIGH. Do not take the Enable1 input to a logic LOW with >VCC volts on the XTAL_IN input.
MOTOROLA
2
TIMING SOLUTIONS
BR1333 — REV 5
MPC903 MPC904 MPC905
AC CHARACTERISTICS
(TA = 0–70°C; VDD = 3.3V
±0.3V)
Symbol
Fmax
tpw
Characteristic
Maximum Operating
Frequency
Output Pulse Width
Using External Crystal
Using External Clock Source
HIGH (Above 2.0V)
LOW (Below 0.8V)
HIGH (Above 2.0V)
LOW (Below 0.8V)
Min
TBD
DC
0.40T
1
0.40T
1
0.45T
2
0.45T
2
T – 400ps
Rising Edges
Falling Edges
1
Enable1
Enable2
Enable1
Enable2
6
30
400
500
4
5
4
4
4
ps
V/ns
ms
Cycles
Cycles
db
Degrees
Series Terminated
Transmission Lines
Typ
Max
50
100
0.60T
1
0.60T
1
0.55T
2
0.55T
2
Unit
MHz
T = Periods
Condition
tper
tos
tr, tf
tEN
tDIS
Aosc
Phase
Output Period
Output-to-Output Skew
Rise/Fall Times (Slew Rate)
Enable Time
Disable Time
XTAL_IN to XTAL_OUT Oscillator Gain
Loop Phase Shift Modulo 360° +
T = Desired Period
1. Assuming input duty cycle specs from Recommended Operationg Conditions table are met.
2. Assuming external crystal or 50% duty cycle external reference is used.
Pin 16
Pin 1
Pin 16
Pin 1
fFUND
CTRAP
+
1
2
p
LTRAP CTRAP
Y1
33.3333MHz
C1
10pF
C3
100Ω
Y1
11.1111MHz
LTRAP
16pF
16pF
C1
10pF
C3
Figure 1. Crystal Oscillator Interface
(Fundamental)
Figure 2. Crystal Oscillator Interface
(3rd Overtone)
Table 1. Crystal Specifications
Parameter
Crystal Cut
Resonance
Frequency Tolerance
Frequency/Temperature Stability
Operating Range
Shunt Capacitance
Equivalent Series Resistance (ESR)
Correlation Drive Level
Aging
Value
Fundamental AT Cut
Parallel Resonance*
±75ppm
at 25°C
±150pm
0 to 70°C
0 to 70°C
5–7pF
50 to 80Ω
100µW
5ppm/Yr (First 3 Years)
TIMING SOLUTIONS
BR1333 — REV 5
3
MOTOROLA
MPC903 MPC904 MPC905
BCLK5
BCLK0–4
ENABLE2
ENABLE1
Figure 3. Enable Timing Diagram
APPLICATIONS INFORMATION
Driving Transmission Lines
The MPC903/904/905 clock driver was designed to drive
high speed signals in a terminated transmission line
environment. To provide the optimum flexibility to the user the
output drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 10Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC903/904/905 clock
driver. For the series terminated case however there is no DC
current draw, thus the outputs can drive multiple series
terminated lines. Figure 4 illustrates an output driving a
single series terminated line vs two series terminated lines in
parallel. When taken to its extreme the fanout of the
MPC903/904/905 clock driver is effectively doubled due to its
capability to drive multiple lines.
MPC903
OUTPUT
BUFFER
IN
7Ω
RS = 43Ω
ZO = 50Ω
OutA
MPC903
OUTPUT
BUFFER
IN
7Ω
RS = 43Ω
ZO = 50Ω
OutB0
RS = 43Ω
ZO = 50Ω
OutB1
Figure 4. Single versus Dual Transmission Lines
The waveform plots of Figure 5 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC903/904/905 output
buffers is more than sufficient to drive 50Ω transmission lines
on the incident edge. Note from the delay measurements in
the simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
MOTOROLA
4
TIMING SOLUTIONS
BR1333 — REV 5
MPC903 MPC904 MPC905
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC903. The output waveform
in Figure 5 shows a step in the waveform, this step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 43Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.8V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
3.0
OutA
tD = 3.8956
OutB
tD = 3.9386
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 6 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
MPC903
OUTPUT
BUFFER
7Ω
RS = 36Ω
ZO = 50Ω
RS = 36Ω
ZO = 50Ω
2.5
VOLTAGE (V)
2.0
In
1.5
7Ω + 36Ω
k
36Ω = 50Ω
k
50Ω
25Ω = 25Ω
Figure 6. Optimized Dual Line Termination
SPICE level output buffer models are available for
engineers who want to simulate their specific interconnect
schemes. In addition IV characteristics are in the process of
being generated to support the other board level simulators in
general use.
1.0
0.5
0
2
4
6
8
TIME (nS)
10
12
14
Figure 5. Single versus Dual Waveforms
TIMING SOLUTIONS
BR1333 — REV 5
5
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