Dear customers,
About the change in the name such as "Oki Electric Industry Co. Ltd." and
"OKI" in documents to OKI Semiconductor Co., Ltd.
The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI
Semiconductor Co., Ltd. on October 1, 2008.
Therefore, please accept that although
the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"
remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".
It is a change of the company name, the company trademark, and the logo, etc. , and
NOT a content change in documents.
October 1, 2008
OKI Semiconductor Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan
http://www.okisemi.com/en/
Semiconductor
MR53V8002J
524,288-Word X 16-Bit or 1,048,576-Word X 8-Bit MASK ROM
This version: Feb. 1999
Previous version: -------
Preliminary
DESCRIPTION
The MR53V8002J is a 8Mbit Read-Only Memory whose configuration can be electrically switched
between 524,288 word x 16bit and 1,048,576 word x 8bit. The MR53V8002J operates asynchronously,
external clocks are not required, making this device easy-to-use. The MR53V8002J is suitable as
large-capacity fixed memory for microcomputers and data terminals. It is manufactured using a CMOS
silicon gate technology and is offered in 42-pin DIP, 44-pin SOP or 44-pin TSOP packages.
FEATURES
· 524,288 word x 16bit / 1,048,576 word x 8bit electrically switchable configuration
· Single +2.7V~3.6V power supply
· Access time
· V
CC
Power supply current
· V
CC
Standby current
· Three-state output
· Packages
42-pin plastic DIP
44-pin plastic SOP
(DIP42-P-600-2.54)
(SOP44-P-600-1.27-K)
MR53V8002J-XXRA
MR53V8002J-XXMA
100ns
40mA
10mA
· Input / Output TTL compatible
44-pin plastic TSOP (TSOPII44-P-400-0.80-K) MR53V8002J-XXTP
1/6
Semiconductor
MR53V8002J
PIN CONFIGURATION (TOP VIEW)
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
42
NC
41
A8
40
A9
39
A10
38
A11
37
A12
36
A13
35
A14
34
A15
33
A16
32
BYTE
31
V
SS
30
D15/A-1
29
D7
28
D14
27
D6
26
D13
25
D5
24
D12
23
D4
22
V
CC
1
2
3
4
5
6
7
8
9
44
NC
43
NC
42
A8
41
A9
40
A10
39
A11
38
A12
37
A13
36
A14
35
A15
34
A16
33
BYTE
32
V
SS
31
D15/A-1
30
D7
29
D14
28
D6
27
D13
26
D5
25
D12
24
D4
23
V
CC
A18
A17
A7
A6
A5
A4
A3
A2
A1
10
A0
11
CE
12
V
SS
13
OE
14
D0
15
D8
15
D1
17
D9
18
D2
19
D10
20
D3
21
D11
22
A0
10
CE
11
V
SS
12
OE
13
D0
14
D8
15
D1
16
D9
17
D2
18
D10
19
D3
20
D11
21
42-Pin DIP
44-Pin SOP
44-Pin TSOPII
PIN NAMES
D15/A-1
A0~A18
D0~D14
CE
OE
BYTE
V
CC
V
SS
NC
FUNCTIONS
Data output / Address input
Address input
Data output
Chip enable
Output enable
Mode switch
Power supply voltage
GND
Non connection
2/6
Semiconductor
MR53V8002J
BLOCK DIAGRAM
A-1
BYTE
X8/X16 SWITCH
CE
OE
CE
OE
CONTROL
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
Row
Decoder
Address
Buffer
Memory Cell
Matrix
524,288 x 16 or 1,048,676 x 8
Column
Decoder
Multiplex
Output Buffer
D0 D1 D2 D3 D4 D5 D6 D7
D8 D9 D10 D11 D12 D13 D14 D15
FUNCTION TABLE
MODE
STAND BY
OUTPUT DISABLE
READ(16-BIT)
READ(8-BIT)
CE
H
L
L
L
L
OE
X
H
H
L
L
BYTE
X
H
L
H
L
D0~D7
D8~D14
Hi-Z
D
OUT
Hi-Z
L/H
L/H
A-1/D15
D
OUT
3/6
Semiconductor
MR53V8002J
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating temperature under bias
Storage temperature
Input voltage
Output voltage
Power supply voltage
Power dissipation per package
Symbol
T
OPR
T
STG
V
I
V
O
V
CC
P
D
Condition
-
-
Relative to V
SS
-
Value
0 ~ 70
-55 ~ 125
-0.5 ~ V
CC
+0.5
-0.5 ~ V
CC
+0.5
-0.5 ~ 5
1.0
Unit
`C
`C
V
V
V
W
RECOMMENDED OPERATING CONDITIONS FOR READ
Parameter
V
CC
power supply voltage
Input “H“ level
Input “L“ level
Voltage is relative to V
SS
Symbol
V
CC
V
IH
V
IL
Condition
V
CC
=2.7V ~ 3.6V
Min.
2.7
2.2
-0.5
Typ.
-
-
-
(Ta=0 ~ 70`C)
Min.
Unit
3.6
`C
V
CC
+0.5
`C
0.8
V
PIN Capacitance
Parameter
Input
Output
Symbol
C
IN
C
OUT
Condition
V
I
=0V
V
O
=0V
(Vcc=3.3V, Ta=25`C, f=1MHz)
Min.
Typ.
Min.
Unit
-
-
12
pF
-
-
15
pF
4/6
