OKI Semiconductor
MS81V32321
1,114,112-Word
×
32-Bit Field Memory
PEDSMS81V32321-02
Issue Date: Mar. 22, 2005
Preliminary
GENERAL DESCRIPTION
The OKI MS81V32321 is a high performance 32-Mbit, 1,100K
×
32-bit, Field Memory. It is especially designed
for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and
Multi-media systems. MS81V32321 is a FRAM for wide or low end use in general commodity TVs and VTRs
exclusively. MS81V32321 is not designed for the other use or high end use in medical systems, professional
graphics systems which require long term picture storage, data storage systems and others.
Each of the 32-bit planes has separate serial write and read ports. These employ independent control clocks to
support asynchronous read and write operations. Different clock rates are also supported that allow alternate data
rates between write and read data streams.
The MS81V32321 provides high speed FIFO, First-In First-Out, operation without external refreshing:
MS81V32321 refreshes its DRAM storage cells automatically, so that it appears fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access
operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the
power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration
logic.
The MS81V32321’s function is simple, and similar to a digital delay device whose delay-bit-length is easily set by
reset timing. The delay length, number of read delay clocks between write and read, is determined by externally
controlled write and read reset timings.
Additionally, the MS81V32321 has write mask function or input enable function (IE), and read-data skipping
function or output enable function (OE) . The differences between write enable (WE) and input enable (IE), and
between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address
increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to
MS81V32321. The input enable (IE) function allows the user to write into selected locations of the memory only,
leaving the rest of the memory contents unchanged. This facilitates data processing to display a “picture in picture”
on a TV screen.
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OKI Semiconductor
MS81V32321
FEATURES
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•
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Single power supply: 3.3 V
±0.3
V
1,114,112 words
×
32 bits
Fast FIFO (First-In First-Out) operation
High speed asynchronous serial access
Read/write cycle time 6.6 ns
Access time
6 ns
Randomly accessible leading address
Variable length delay bit (350 to 1,114,112)
Write/Read start address settable
Write mask function (Input enable control)
Data skipping function (Output enable control)
Self refresh (No refresh control is required)
SSTL-3 compatible inputs and outputs
Package options:
128-pin plastic TQFP
(TQFP128-P-1414-0.40-K)
(MS81V32321-xxTB)
xx indicates speed rank.
PRODUCT FAMILY
Family
MS81V32321-66TB
MS81V32321-7TB
Access Time (Max.)
6 ns
6.5 ns
Cycle Time (Min.)
6.6 ns (150 MHz)
7 ns (143 MHz)
Package
128-pin TQFP
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MS81V32321
PIN CONFIGURATION (TOP VIEW)
DO1
DO0
V
SS
Q
V
CC
Q
V
SS
DI7
DI6
DI5
DI4
V
CC
DI3
DI2
DI1
DI0
V
SS
V
CC
V
REF
V
SS
DI31
DI30
DI29
DI28
V
CC
DI27
DI26
DI25
DI24
V
SS
V
CC
Q
V
SS
Q
DO31
DO30
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
V
CC
Q
DO2
DO3
V
SS
Q
V
CC
DO4
DO5
V
CC
Q
DO6
DO7
V
SS
Q
V
SS
SWCK
RSTW
V
CC
V
SS
V
CC
WE
IE
WAD
V
SS
V
SS
Q
DO8
DO9
V
CC
Q
DO10
DO11
V
CC
V
SS
Q
DO12
DO13
V
CC
Q
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
V
CC
Q
DO29
DO28
V
SS
Q
V
CC
DO27
DO26
V
CC
Q
DO25
DO24
V
SS
Q
V
SS
SRCK
RSTR
V
CC
V
SS
V
CC
RE
OE
RAD
V
SS
V
SS
Q
DO23
DO22
V
CC
Q
DO21
DO20
V
CC
V
SS
Q
DO19
DO18
V
CC
Q
Pin Name
SWCK
SRCK
WE
RE
IE
OE
RSTW
RSTR
WAD
Note: The same power supply voltage must be provided to every V
CC
pin and V
CC
Q pin, and the same
GND voltage level must be provided to every V
SS
pin and V
SS
Q pin.
DO14
ＤＯ15
V
SS
Q
V
CC
Q
V
SS
DI8
DI9
DI10
DI11
V
CC
DI12
DI13
DI14
DI15
V
SS
V
CC
V
SS
V
SS
DI16
DI17
DI18
DI19
V
CC
DI20
DI21
DI22
DI23
V
SS
V
CC
Q
V
SS
Q
DO16
DO17
128-Pin TQFP
Function
Serial Write Clock
Serial Read Clock
Write Enable
Read Enable
Input Enable
Output Enable
Write Reset Clock
Read Reset Clock
Write Address Input
Pin Name
RAD
DI0 to 31
DO0 to 31
V
CC
V
SS
V
CC
Q
V
SS
Q
V
REF
Function
Read Address Input
Data Input
Data Output
Power Supply (3.3 V)
Ground (0 V)
Power Supply for output
Ground for output
Input Reference Voltage
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PEDS81V32321-02
OKI Semiconductor
MS81V32321
BLOCK DIAGRAM
DO (X32)
OE
RE
RSTR
SRCK
Data-output
Buffer
Serial Read Controller
Read Data Register
(X32)
1,114,112 x 32
Memory
Array
X
Decoder
Read/Write
Refresh
Timing Generater
(X32)
Write Data Register
Refresh
Counter
Data-input
Buffer
Serial Write Controller
DI (X32)
IE
WE
RSTW
SWCK
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OKI Semiconductor
MS81V32321
PIN DESCRIPTION
Serial Write Clock: SWCK
The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer.
Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK.
Write Reset: RSTW
RSTW is used to set the internal write address pointer. RSTW setup and hold times are referenced to the rising
edge of SWCK. The SWCK latches the write address data (21bits serial LSB) from WAD.
Write Enable: WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the
input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high)
restrictions, because the MS81V32321 is in fully static operation as long as the power is on. Note that WE setup
and hold times are referenced to the rising edge of SWCK. The latency for the write operation control by WE is 4.
After write reset, WE must remain low for more than 1600 ns (tFWD). After write reset, the write operation at
address 0 is started after a time tWL form the cycle in which WE is brought high.
After write reset, WE should be remained high for 2 cycles after driving WE high first.
Input Enable: IE
IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address pointer
is always incremented by cycling SWCK regardless of the IE level. Note that IE setup and hold times are
referenced to the rising edge of SWCK. The latency for the write operation control by IE is 4.
Write Address Input: WAD
These pins are used for write address input.
Data Inputs: (DI0-31)
These pins are used for serial data inputs.
Write Reset: RSTW
RSTW is used to set the internal write address pointer. RSTW setup and hold times are referenced to the rising
edge of SWCK. The SWCK latches the write address data (21bits serial LSB) from WAD.
Data Out: (DO0-31)
These pins are used for serial data outputs.
Serial Read Clock: SRCK
Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read
operation. The SRCK input increments the internal read address pointer when RE is high.
The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same
polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of
SRCK. *There are no output valid time restriction on MS81V32321.
Read Reset: RSTR
RSTR is used to set the internal read address pointer. RSTR setup and hold times are referenced to the rising edge
of SRCK. The SWCK latches the read address data (21bits serial LSB) from RAD.
Read Enable: RE
The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is high before the
rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not incremented. RE
setup times (tRENS and tRDSS) and RE hold times (tRENH and tRDSH) are referenced to the rising edge of the
SRCK clock.
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